tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1LVDS Display Panel
2==================
3
4LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
5incompatible data link layers have been used over time to transmit image data
6to LVDS panels. This bindings supports display panels compatible with the
7following specifications.
8
9[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
101999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
11[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
12Semiconductor
13[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
14Electronics Standards Association (VESA)
15
16Device compatible with those specifications have been marketed under the
17FPD-Link and FlatLink brands.
18
19
20Required properties:
21
22- compatible: Shall contain "panel-lvds" in addition to a mandatory
23 panel-specific compatible string defined in individual panel bindings. The
24 "panel-lvds" value shall never be used on its own.
25- width-mm: See panel-common.txt.
26- height-mm: See panel-common.txt.
27- data-mapping: The color signals mapping order, "jeida-18", "jeida-24"
28 or "vesa-24".
29
30Optional properties:
31
32- label: See panel-common.txt.
33- gpios: See panel-common.txt.
34- backlight: See panel-common.txt.
35- power-supply: See panel-common.txt.
36- data-mirror: If set, reverse the bit order described in the data mappings
37 below on all data lanes, transmitting bits for slots 6 to 0 instead of
38 0 to 6.
39
40Required nodes:
41
42- panel-timing: See panel-common.txt.
43- ports: See panel-common.txt. These bindings require a single port subnode
44 corresponding to the panel LVDS input.
45
46
47LVDS data mappings are defined as follows.
48
49- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
50 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
51
52Slot 0 1 2 3 4 5 6
53 ________________ _________________
54Clock \_______________________/
55 ______ ______ ______ ______ ______ ______ ______
56DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
57DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
58DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
59
60- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
61 specifications. Data are transferred as follows on 4 LVDS lanes.
62
63Slot 0 1 2 3 4 5 6
64 ________________ _________________
65Clock \_______________________/
66 ______ ______ ______ ______ ______ ______ ______
67DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
68DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
69DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
70DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
71
72- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
73 Data are transferred as follows on 4 LVDS lanes.
74
75Slot 0 1 2 3 4 5 6
76 ________________ _________________
77Clock \_______________________/
78 ______ ______ ______ ______ ______ ______ ______
79DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
80DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
81DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
82DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
83
84Control signals are mapped as follows.
85
86CTL0: HSync
87CTL1: VSync
88CTL2: Data Enable
89CTL3: 0
90
91
92Example
93-------
94
95panel {
96 compatible = "mitsubishi,aa121td01", "panel-lvds";
97
98 width-mm = <261>;
99 height-mm = <163>;
100
101 data-mapping = "jeida-24";
102
103 panel-timing {
104 /* 1280x800 @60Hz */
105 clock-frequency = <71000000>;
106 hactive = <1280>;
107 vactive = <800>;
108 hsync-len = <70>;
109 hfront-porch = <20>;
110 hback-porch = <70>;
111 vsync-len = <5>;
112 vfront-porch = <3>;
113 vback-porch = <15>;
114 };
115
116 port {
117 panel_in: endpoint {
118 remote-endpoint = <&lvds_encoder>;
119 };
120 };
121};