tjh.dev / kernel
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kernel / drivers / net / ethernet / engleder / tsnep_hw.h
at v5.19 235 lines 7.1 kB view raw
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (C) 2021 Gerhard Engleder <gerhard@engleder-embedded.com> */ 3 4/* Hardware definition of TSNEP and EtherCAT MAC device */ 5 6#ifndef _TSNEP_HW_H 7#define _TSNEP_HW_H 8 9#include <linux/types.h> 10 11/* type */ 12#define ECM_TYPE 0x0000 13#define ECM_REVISION_MASK 0x000000FF 14#define ECM_REVISION_SHIFT 0 15#define ECM_VERSION_MASK 0x0000FF00 16#define ECM_VERSION_SHIFT 8 17#define ECM_QUEUE_COUNT_MASK 0x00070000 18#define ECM_QUEUE_COUNT_SHIFT 16 19#define ECM_GATE_CONTROL 0x02000000 20 21/* system time */ 22#define ECM_SYSTEM_TIME_LOW 0x0008 23#define ECM_SYSTEM_TIME_HIGH 0x000C 24 25/* clock */ 26#define ECM_CLOCK_RATE 0x0010 27#define ECM_CLOCK_RATE_OFFSET_MASK 0x7FFFFFFF 28#define ECM_CLOCK_RATE_OFFSET_SIGN 0x80000000 29 30/* interrupt */ 31#define ECM_INT_ENABLE 0x0018 32#define ECM_INT_ACTIVE 0x001C 33#define ECM_INT_ACKNOWLEDGE 0x001C 34#define ECM_INT_LINK 0x00000020 35#define ECM_INT_TX_0 0x00000100 36#define ECM_INT_RX_0 0x00000200 37#define ECM_INT_ALL 0x7FFFFFFF 38#define ECM_INT_DISABLE 0x80000000 39 40/* reset */ 41#define ECM_RESET 0x0020 42#define ECM_RESET_COMMON 0x00000001 43#define ECM_RESET_CHANNEL 0x00000100 44#define ECM_RESET_TXRX 0x00010000 45 46/* counter */ 47#define ECM_COUNTER_LOW 0x0028 48#define ECM_COUNTER_HIGH 0x002C 49 50/* control and status */ 51#define ECM_STATUS 0x0080 52#define ECM_LINK_MODE_OFF 0x01000000 53#define ECM_LINK_MODE_100 0x02000000 54#define ECM_LINK_MODE_1000 0x04000000 55#define ECM_NO_LINK 0x01000000 56#define ECM_LINK_MODE_MASK 0x06000000 57 58/* management data */ 59#define ECM_MD_CONTROL 0x0084 60#define ECM_MD_STATUS 0x0084 61#define ECM_MD_PREAMBLE 0x00000001 62#define ECM_MD_READ 0x00000004 63#define ECM_MD_WRITE 0x00000002 64#define ECM_MD_ADDR_MASK 0x000000F8 65#define ECM_MD_ADDR_SHIFT 3 66#define ECM_MD_PHY_ADDR_MASK 0x00001F00 67#define ECM_MD_PHY_ADDR_SHIFT 8 68#define ECM_MD_BUSY 0x00000001 69#define ECM_MD_DATA_MASK 0xFFFF0000 70#define ECM_MD_DATA_SHIFT 16 71 72/* statistic */ 73#define ECM_STAT 0x00B0 74#define ECM_STAT_RX_ERR_MASK 0x000000FF 75#define ECM_STAT_RX_ERR_SHIFT 0 76#define ECM_STAT_INV_FRM_MASK 0x0000FF00 77#define ECM_STAT_INV_FRM_SHIFT 8 78#define ECM_STAT_FWD_RX_ERR_MASK 0x00FF0000 79#define ECM_STAT_FWD_RX_ERR_SHIFT 16 80 81/* tsnep */ 82#define TSNEP_MAC_SIZE 0x4000 83#define TSNEP_QUEUE_SIZE 0x1000 84#define TSNEP_QUEUE(n) ({ typeof(n) __n = (n); \ 85 (__n) == 0 ? \ 86 0 : \ 87 TSNEP_MAC_SIZE + TSNEP_QUEUE_SIZE * ((__n) - 1); }) 88#define TSNEP_MAX_QUEUES 8 89#define TSNEP_MAX_FRAME_SIZE (2 * 1024) /* hardware supports actually 16k */ 90#define TSNEP_DESC_SIZE 256 91#define TSNEP_DESC_OFFSET 128 92 93/* tsnep register */ 94#define TSNEP_INFO 0x0100 95#define TSNEP_INFO_RX_ASSIGN 0x00010000 96#define TSNEP_INFO_TX_TIME 0x00020000 97#define TSNEP_CONTROL 0x0108 98#define TSNEP_CONTROL_TX_RESET 0x00000001 99#define TSNEP_CONTROL_TX_ENABLE 0x00000002 100#define TSNEP_CONTROL_TX_DMA_ERROR 0x00000010 101#define TSNEP_CONTROL_TX_DESC_ERROR 0x00000020 102#define TSNEP_CONTROL_RX_RESET 0x00000100 103#define TSNEP_CONTROL_RX_ENABLE 0x00000200 104#define TSNEP_CONTROL_RX_DISABLE 0x00000400 105#define TSNEP_CONTROL_RX_DMA_ERROR 0x00001000 106#define TSNEP_CONTROL_RX_DESC_ERROR 0x00002000 107#define TSNEP_TX_DESC_ADDR_LOW 0x0140 108#define TSNEP_TX_DESC_ADDR_HIGH 0x0144 109#define TSNEP_RX_DESC_ADDR_LOW 0x0180 110#define TSNEP_RX_DESC_ADDR_HIGH 0x0184 111#define TSNEP_RESET_OWNER_COUNTER 0x01 112#define TSNEP_RX_STATISTIC 0x0190 113#define TSNEP_RX_STATISTIC_NO_DESC_MASK 0x000000FF 114#define TSNEP_RX_STATISTIC_NO_DESC_SHIFT 0 115#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_MASK 0x0000FF00 116#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL_SHIFT 8 117#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_MASK 0x00FF0000 118#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW_SHIFT 16 119#define TSNEP_RX_STATISTIC_INVALID_FRAME_MASK 0xFF000000 120#define TSNEP_RX_STATISTIC_INVALID_FRAME_SHIFT 24 121#define TSNEP_RX_STATISTIC_NO_DESC 0x0190 122#define TSNEP_RX_STATISTIC_BUFFER_TOO_SMALL 0x0191 123#define TSNEP_RX_STATISTIC_FIFO_OVERFLOW 0x0192 124#define TSNEP_RX_STATISTIC_INVALID_FRAME 0x0193 125#define TSNEP_RX_ASSIGN 0x01A0 126#define TSNEP_RX_ASSIGN_ETHER_TYPE_ACTIVE 0x00000001 127#define TSNEP_RX_ASSIGN_ETHER_TYPE_MASK 0xFFFF0000 128#define TSNEP_RX_ASSIGN_ETHER_TYPE_SHIFT 16 129#define TSNEP_MAC_ADDRESS_LOW 0x0800 130#define TSNEP_MAC_ADDRESS_HIGH 0x0804 131#define TSNEP_RX_FILTER 0x0806 132#define TSNEP_RX_FILTER_ACCEPT_ALL_MULTICASTS 0x0001 133#define TSNEP_RX_FILTER_ACCEPT_ALL_UNICASTS 0x0002 134#define TSNEP_GC 0x0808 135#define TSNEP_GC_ENABLE_A 0x00000002 136#define TSNEP_GC_ENABLE_B 0x00000004 137#define TSNEP_GC_DISABLE 0x00000008 138#define TSNEP_GC_ENABLE_TIMEOUT 0x00000010 139#define TSNEP_GC_ACTIVE_A 0x00000002 140#define TSNEP_GC_ACTIVE_B 0x00000004 141#define TSNEP_GC_CHANGE_AB 0x00000008 142#define TSNEP_GC_TIMEOUT_ACTIVE 0x00000010 143#define TSNEP_GC_TIMEOUT_SIGNAL 0x00000020 144#define TSNEP_GC_LIST_ERROR 0x00000080 145#define TSNEP_GC_OPEN 0x00FF0000 146#define TSNEP_GC_OPEN_SHIFT 16 147#define TSNEP_GC_NEXT_OPEN 0xFF000000 148#define TSNEP_GC_NEXT_OPEN_SHIFT 24 149#define TSNEP_GC_TIMEOUT 131072 150#define TSNEP_GC_TIME 0x080C 151#define TSNEP_GC_CHANGE 0x0810 152#define TSNEP_GCL_A 0x2000 153#define TSNEP_GCL_B 0x2800 154#define TSNEP_GCL_SIZE SZ_2K 155 156/* tsnep gate control list operation */ 157struct tsnep_gcl_operation { 158 u32 properties; 159 u32 interval; 160}; 161 162#define TSNEP_GCL_COUNT (TSNEP_GCL_SIZE / sizeof(struct tsnep_gcl_operation)) 163#define TSNEP_GCL_MASK 0x000000FF 164#define TSNEP_GCL_INSERT 0x20000000 165#define TSNEP_GCL_CHANGE 0x40000000 166#define TSNEP_GCL_LAST 0x80000000 167#define TSNEP_GCL_MIN_INTERVAL 32 168 169/* tsnep TX/RX descriptor */ 170#define TSNEP_DESC_SIZE 256 171#define TSNEP_DESC_SIZE_DATA_AFTER 2048 172#define TSNEP_DESC_OFFSET 128 173#define TSNEP_DESC_OWNER_COUNTER_MASK 0xC0000000 174#define TSNEP_DESC_OWNER_COUNTER_SHIFT 30 175#define TSNEP_DESC_LENGTH_MASK 0x00003FFF 176#define TSNEP_DESC_INTERRUPT_FLAG 0x00040000 177#define TSNEP_DESC_EXTENDED_WRITEBACK_FLAG 0x00080000 178#define TSNEP_DESC_NO_LINK_FLAG 0x01000000 179 180/* tsnep TX descriptor */ 181struct tsnep_tx_desc { 182 __le32 properties; 183 __le32 more_properties; 184 __le32 reserved[2]; 185 __le64 next; 186 __le64 tx; 187}; 188 189#define TSNEP_TX_DESC_OWNER_MASK 0xE0000000 190#define TSNEP_TX_DESC_OWNER_USER_FLAG 0x20000000 191#define TSNEP_TX_DESC_LAST_FRAGMENT_FLAG 0x00010000 192#define TSNEP_TX_DESC_DATA_AFTER_DESC_FLAG 0x00020000 193 194/* tsnep TX descriptor writeback */ 195struct tsnep_tx_desc_wb { 196 __le32 properties; 197 __le32 reserved1; 198 __le64 counter; 199 __le64 timestamp; 200 __le32 dma_delay; 201 __le32 reserved2; 202}; 203 204#define TSNEP_TX_DESC_UNDERRUN_ERROR_FLAG 0x00010000 205#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_MASK 0x0000FFFC 206#define TSNEP_TX_DESC_DMA_DELAY_FIRST_DATA_SHIFT 2 207#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_MASK 0xFFFC0000 208#define TSNEP_TX_DESC_DMA_DELAY_LAST_DATA_SHIFT 18 209#define TSNEP_TX_DESC_DMA_DELAY_NS 64 210 211/* tsnep RX descriptor */ 212struct tsnep_rx_desc { 213 __le32 properties; 214 __le32 reserved[3]; 215 __le64 next; 216 __le64 rx; 217}; 218 219#define TSNEP_RX_DESC_BUFFER_SIZE_MASK 0x00003FFC 220 221/* tsnep RX descriptor writeback */ 222struct tsnep_rx_desc_wb { 223 __le32 properties; 224 __le32 reserved[7]; 225}; 226 227/* tsnep RX inline meta */ 228struct tsnep_rx_inline { 229 __le64 counter; 230 __le64 timestamp; 231}; 232 233#define TSNEP_RX_INLINE_METADATA_SIZE (sizeof(struct tsnep_rx_inline)) 234 235#endif /* _TSNEP_HW_H */