tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Genesys Logic, Inc.
4 *
5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6 *
7 * Version: v0.9.0 (2019-08-08)
8 */
9
10#include <linux/bitfield.h>
11#include <linux/bits.h>
12#include <linux/pci.h>
13#include <linux/mmc/mmc.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/iopoll.h>
17#include "sdhci.h"
18#include "sdhci-pci.h"
19#include "cqhci.h"
20
21/* Genesys Logic extra registers */
22#define SDHCI_GLI_9750_WT 0x800
23#define SDHCI_GLI_9750_WT_EN BIT(0)
24#define GLI_9750_WT_EN_ON 0x1
25#define GLI_9750_WT_EN_OFF 0x0
26
27#define SDHCI_GLI_9750_CFG2 0x848
28#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
29#define GLI_9750_CFG2_L1DLY_VALUE 0x1F
30
31#define SDHCI_GLI_9750_DRIVING 0x860
32#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
33#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
34#define GLI_9750_DRIVING_1_VALUE 0xFFF
35#define GLI_9750_DRIVING_2_VALUE 0x3
36#define SDHCI_GLI_9750_SEL_1 BIT(29)
37#define SDHCI_GLI_9750_SEL_2 BIT(31)
38#define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
39
40#define SDHCI_GLI_9750_PLL 0x864
41#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
42#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
43#define SDHCI_GLI_9750_PLL_DIR BIT(15)
44#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
45#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
46#define GLI_9750_PLL_TX2_INV_VALUE 0x1
47#define GLI_9750_PLL_TX2_DLY_VALUE 0x0
48#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
49#define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
50
51#define SDHCI_GLI_9750_PLLSSC 0x86C
52#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
53
54#define SDHCI_GLI_9750_SW_CTRL 0x874
55#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
56#define GLI_9750_SW_CTRL_4_VALUE 0x3
57
58#define SDHCI_GLI_9750_MISC 0x878
59#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
60#define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
61#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
62#define GLI_9750_MISC_TX1_INV_VALUE 0x0
63#define GLI_9750_MISC_RX_INV_ON 0x1
64#define GLI_9750_MISC_RX_INV_OFF 0x0
65#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
66#define GLI_9750_MISC_TX1_DLY_VALUE 0x5
67#define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)
68
69#define SDHCI_GLI_9750_TUNING_CONTROL 0x540
70#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
71#define GLI_9750_TUNING_CONTROL_EN_ON 0x1
72#define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
73#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
74#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
75#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
76#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
77
78#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
79#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
80#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
81
82#define SDHCI_GLI_9763E_CTRL_HS400 0x7
83
84#define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
85#define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
86
87#define PCIE_GLI_9763E_VHS 0x884
88#define GLI_9763E_VHS_REV GENMASK(19, 16)
89#define GLI_9763E_VHS_REV_R 0x0
90#define GLI_9763E_VHS_REV_M 0x1
91#define GLI_9763E_VHS_REV_W 0x2
92#define PCIE_GLI_9763E_MB 0x888
93#define GLI_9763E_MB_CMDQ_OFF BIT(19)
94#define GLI_9763E_MB_ERP_ON BIT(7)
95#define PCIE_GLI_9763E_SCR 0x8E0
96#define GLI_9763E_SCR_AXI_REQ BIT(9)
97
98#define PCIE_GLI_9763E_CFG2 0x8A4
99#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
100#define GLI_9763E_CFG2_L1DLY_MID 0x54
101
102#define PCIE_GLI_9763E_MMC_CTRL 0x960
103#define GLI_9763E_HS400_SLOW BIT(3)
104
105#define PCIE_GLI_9763E_CLKRXDLY 0x934
106#define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
107#define GLI_9763E_HS400_RXDLY_5 0x5
108
109#define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
110#define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
111 SDHCI_TRNS_BLK_CNT_EN | \
112 SDHCI_TRNS_DMA)
113
114#define PCI_GLI_9755_WT 0x800
115#define PCI_GLI_9755_WT_EN BIT(0)
116#define GLI_9755_WT_EN_ON 0x1
117#define GLI_9755_WT_EN_OFF 0x0
118
119#define PCI_GLI_9755_PECONF 0x44
120#define PCI_GLI_9755_LFCLK GENMASK(14, 12)
121#define PCI_GLI_9755_DMACLK BIT(29)
122#define PCI_GLI_9755_INVERT_CD BIT(30)
123#define PCI_GLI_9755_INVERT_WP BIT(31)
124
125#define PCI_GLI_9755_CFG2 0x48
126#define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
127#define GLI_9755_CFG2_L1DLY_VALUE 0x1F
128
129#define PCI_GLI_9755_PLL 0x64
130#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
131#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
132#define PCI_GLI_9755_PLL_DIR BIT(15)
133#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
134#define PCI_GLI_9755_PLLSSC_EN BIT(31)
135
136#define PCI_GLI_9755_PLLSSC 0x68
137#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
138
139#define PCI_GLI_9755_SerDes 0x70
140#define PCI_GLI_9755_SCP_DIS BIT(19)
141
142#define PCI_GLI_9755_MISC 0x78
143#define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
144
145#define PCI_GLI_9755_PM_CTRL 0xFC
146#define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
147
148#define GLI_MAX_TUNING_LOOP 40
149
150/* Genesys Logic chipset */
151static inline void gl9750_wt_on(struct sdhci_host *host)
152{
153 u32 wt_value;
154 u32 wt_enable;
155
156 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
157 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
158
159 if (wt_enable == GLI_9750_WT_EN_ON)
160 return;
161
162 wt_value &= ~SDHCI_GLI_9750_WT_EN;
163 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
164
165 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
166}
167
168static inline void gl9750_wt_off(struct sdhci_host *host)
169{
170 u32 wt_value;
171 u32 wt_enable;
172
173 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
174 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
175
176 if (wt_enable == GLI_9750_WT_EN_OFF)
177 return;
178
179 wt_value &= ~SDHCI_GLI_9750_WT_EN;
180 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
181
182 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
183}
184
185static void gli_set_9750(struct sdhci_host *host)
186{
187 u32 driving_value;
188 u32 pll_value;
189 u32 sw_ctrl_value;
190 u32 misc_value;
191 u32 parameter_value;
192 u32 control_value;
193 u16 ctrl2;
194
195 gl9750_wt_on(host);
196
197 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
198 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
199 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
200 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
201 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
202 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
203
204 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
205 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
206 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
207 GLI_9750_DRIVING_1_VALUE);
208 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
209 GLI_9750_DRIVING_2_VALUE);
210 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
211 driving_value |= SDHCI_GLI_9750_SEL_2;
212 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
213
214 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
215 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
216 GLI_9750_SW_CTRL_4_VALUE);
217 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
218
219 /* reset the tuning flow after reinit and before starting tuning */
220 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
221 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
222 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
223 GLI_9750_PLL_TX2_INV_VALUE);
224 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
225 GLI_9750_PLL_TX2_DLY_VALUE);
226
227 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
228 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
229 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
230 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
231 GLI_9750_MISC_TX1_INV_VALUE);
232 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
233 GLI_9750_MISC_RX_INV_VALUE);
234 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
235 GLI_9750_MISC_TX1_DLY_VALUE);
236
237 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
238 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
239 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
240
241 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
242 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
243 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
244 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
245 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
246 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
247
248 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
249 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
250
251 /* disable tuned clk */
252 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
253 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
254 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
255
256 /* enable tuning parameters control */
257 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
258 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
259 GLI_9750_TUNING_CONTROL_EN_ON);
260 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
261
262 /* write tuning parameters */
263 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
264
265 /* disable tuning parameters control */
266 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
267 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
268 GLI_9750_TUNING_CONTROL_EN_OFF);
269 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
270
271 /* clear tuned clk */
272 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
273 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
274 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
275
276 gl9750_wt_off(host);
277}
278
279static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
280{
281 u32 misc_value;
282
283 gl9750_wt_on(host);
284
285 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
286 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
287 if (b) {
288 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
289 GLI_9750_MISC_RX_INV_ON);
290 } else {
291 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
292 GLI_9750_MISC_RX_INV_OFF);
293 }
294 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
295
296 gl9750_wt_off(host);
297}
298
299static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
300{
301 int i;
302 int rx_inv;
303
304 for (rx_inv = 0; rx_inv < 2; rx_inv++) {
305 gli_set_9750_rx_inv(host, !!rx_inv);
306 sdhci_start_tuning(host);
307
308 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
309 u16 ctrl;
310
311 sdhci_send_tuning(host, opcode);
312
313 if (!host->tuning_done) {
314 sdhci_abort_tuning(host, opcode);
315 break;
316 }
317
318 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
319 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
320 if (ctrl & SDHCI_CTRL_TUNED_CLK)
321 return 0; /* Success! */
322 break;
323 }
324 }
325 }
326 if (!host->tuning_done) {
327 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
328 mmc_hostname(host->mmc));
329 return -ETIMEDOUT;
330 }
331
332 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
333 mmc_hostname(host->mmc));
334 sdhci_reset_tuning(host);
335
336 return -EAGAIN;
337}
338
339static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
340{
341 host->mmc->retune_period = 0;
342 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
343 host->mmc->retune_period = host->tuning_count;
344
345 gli_set_9750(host);
346 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
347 sdhci_end_tuning(host);
348
349 return 0;
350}
351
352static void gl9750_disable_ssc_pll(struct sdhci_host *host)
353{
354 u32 pll;
355
356 gl9750_wt_on(host);
357 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
358 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
359 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
360 gl9750_wt_off(host);
361}
362
363static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
364{
365 u32 pll;
366
367 gl9750_wt_on(host);
368 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
369 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
370 SDHCI_GLI_9750_PLL_PDIV |
371 SDHCI_GLI_9750_PLL_DIR);
372 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
373 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
374 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
375 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
376 gl9750_wt_off(host);
377
378 /* wait for pll stable */
379 mdelay(1);
380}
381
382static bool gl9750_ssc_enable(struct sdhci_host *host)
383{
384 u32 misc;
385 u8 off;
386
387 gl9750_wt_on(host);
388 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
389 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
390 gl9750_wt_off(host);
391
392 return !off;
393}
394
395static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
396{
397 u32 pll;
398 u32 ssc;
399
400 gl9750_wt_on(host);
401 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
402 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
403 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
404 SDHCI_GLI_9750_PLLSSC_EN);
405 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
406 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
407 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
408 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
409 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
410 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
411 gl9750_wt_off(host);
412}
413
414static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
415{
416 bool enable = gl9750_ssc_enable(host);
417
418 /* set pll to 205MHz and ssc */
419 gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
420 gl9750_set_pll(host, 0x1, 0x246, 0x0);
421}
422
423static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
424{
425 bool enable = gl9750_ssc_enable(host);
426
427 /* set pll to 100MHz and ssc */
428 gl9750_set_ssc(host, enable, 0xE, 0x51EC);
429 gl9750_set_pll(host, 0x1, 0x244, 0x1);
430}
431
432static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
433{
434 bool enable = gl9750_ssc_enable(host);
435
436 /* set pll to 50MHz and ssc */
437 gl9750_set_ssc(host, enable, 0xE, 0x51EC);
438 gl9750_set_pll(host, 0x1, 0x244, 0x3);
439}
440
441static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
442{
443 struct mmc_ios *ios = &host->mmc->ios;
444 u16 clk;
445
446 host->mmc->actual_clock = 0;
447
448 gl9750_disable_ssc_pll(host);
449 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
450
451 if (clock == 0)
452 return;
453
454 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
455 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
456 host->mmc->actual_clock = 205000000;
457 gl9750_set_ssc_pll_205mhz(host);
458 } else if (clock == 100000000) {
459 gl9750_set_ssc_pll_100mhz(host);
460 } else if (clock == 50000000) {
461 gl9750_set_ssc_pll_50mhz(host);
462 }
463
464 sdhci_enable_clk(host, clk);
465}
466
467static void gl9750_hw_setting(struct sdhci_host *host)
468{
469 u32 value;
470
471 gl9750_wt_on(host);
472
473 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
474 value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
475 /* set ASPM L1 entry delay to 7.9us */
476 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
477 GLI_9750_CFG2_L1DLY_VALUE);
478 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
479
480 gl9750_wt_off(host);
481}
482
483static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
484{
485 int ret;
486
487 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
488 PCI_IRQ_MSI | PCI_IRQ_MSIX);
489 if (ret < 0) {
490 pr_warn("%s: enable PCI MSI failed, error=%d\n",
491 mmc_hostname(slot->host->mmc), ret);
492 return;
493 }
494
495 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
496}
497
498static inline void gl9755_wt_on(struct pci_dev *pdev)
499{
500 u32 wt_value;
501 u32 wt_enable;
502
503 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
504 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
505
506 if (wt_enable == GLI_9755_WT_EN_ON)
507 return;
508
509 wt_value &= ~PCI_GLI_9755_WT_EN;
510 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
511
512 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
513}
514
515static inline void gl9755_wt_off(struct pci_dev *pdev)
516{
517 u32 wt_value;
518 u32 wt_enable;
519
520 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
521 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
522
523 if (wt_enable == GLI_9755_WT_EN_OFF)
524 return;
525
526 wt_value &= ~PCI_GLI_9755_WT_EN;
527 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
528
529 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
530}
531
532static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
533{
534 u32 pll;
535
536 gl9755_wt_on(pdev);
537 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
538 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
539 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
540 gl9755_wt_off(pdev);
541}
542
543static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
544{
545 u32 pll;
546
547 gl9755_wt_on(pdev);
548 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
549 pll &= ~(PCI_GLI_9755_PLL_LDIV |
550 PCI_GLI_9755_PLL_PDIV |
551 PCI_GLI_9755_PLL_DIR);
552 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
553 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
554 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
555 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
556 gl9755_wt_off(pdev);
557
558 /* wait for pll stable */
559 mdelay(1);
560}
561
562static bool gl9755_ssc_enable(struct pci_dev *pdev)
563{
564 u32 misc;
565 u8 off;
566
567 gl9755_wt_on(pdev);
568 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
569 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
570 gl9755_wt_off(pdev);
571
572 return !off;
573}
574
575static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
576{
577 u32 pll;
578 u32 ssc;
579
580 gl9755_wt_on(pdev);
581 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
582 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
583 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
584 PCI_GLI_9755_PLLSSC_EN);
585 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
586 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
587 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
588 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
589 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
590 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
591 gl9755_wt_off(pdev);
592}
593
594static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
595{
596 bool enable = gl9755_ssc_enable(pdev);
597
598 /* set pll to 205MHz and ssc */
599 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
600 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
601}
602
603static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
604{
605 bool enable = gl9755_ssc_enable(pdev);
606
607 /* set pll to 100MHz and ssc */
608 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
609 gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
610}
611
612static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
613{
614 bool enable = gl9755_ssc_enable(pdev);
615
616 /* set pll to 50MHz and ssc */
617 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
618 gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
619}
620
621static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
622{
623 struct sdhci_pci_slot *slot = sdhci_priv(host);
624 struct mmc_ios *ios = &host->mmc->ios;
625 struct pci_dev *pdev;
626 u16 clk;
627
628 pdev = slot->chip->pdev;
629 host->mmc->actual_clock = 0;
630
631 gl9755_disable_ssc_pll(pdev);
632 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
633
634 if (clock == 0)
635 return;
636
637 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
638 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
639 host->mmc->actual_clock = 205000000;
640 gl9755_set_ssc_pll_205mhz(pdev);
641 } else if (clock == 100000000) {
642 gl9755_set_ssc_pll_100mhz(pdev);
643 } else if (clock == 50000000) {
644 gl9755_set_ssc_pll_50mhz(pdev);
645 }
646
647 sdhci_enable_clk(host, clk);
648}
649
650static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
651{
652 struct pci_dev *pdev = slot->chip->pdev;
653 u32 value;
654
655 gl9755_wt_on(pdev);
656
657 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
658 /*
659 * Apple ARM64 platforms using these chips may have
660 * inverted CD/WP detection.
661 */
662 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
663 value |= PCI_GLI_9755_INVERT_CD;
664 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
665 value |= PCI_GLI_9755_INVERT_WP;
666 value &= ~PCI_GLI_9755_LFCLK;
667 value &= ~PCI_GLI_9755_DMACLK;
668 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
669
670 /* enable short circuit protection */
671 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
672 value &= ~PCI_GLI_9755_SCP_DIS;
673 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
674
675 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
676 value &= ~PCI_GLI_9755_CFG2_L1DLY;
677 /* set ASPM L1 entry delay to 7.9us */
678 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
679 GLI_9755_CFG2_L1DLY_VALUE);
680 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
681
682 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
683 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
684 value |= PCI_GLI_9755_PM_STATE;
685 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
686 value &= ~PCI_GLI_9755_PM_STATE;
687 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
688
689 gl9755_wt_off(pdev);
690}
691
692static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
693{
694 struct sdhci_host *host = slot->host;
695
696 gl9750_hw_setting(host);
697 gli_pcie_enable_msi(slot);
698 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
699 sdhci_enable_v4_mode(host);
700
701 return 0;
702}
703
704static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
705{
706 struct sdhci_host *host = slot->host;
707
708 gl9755_hw_setting(slot);
709 gli_pcie_enable_msi(slot);
710 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
711 sdhci_enable_v4_mode(host);
712
713 return 0;
714}
715
716static void sdhci_gli_voltage_switch(struct sdhci_host *host)
717{
718 /*
719 * According to Section 3.6.1 signal voltage switch procedure in
720 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
721 * follows:
722 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
723 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
724 * period.
725 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
726 * step (12).
727 *
728 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
729 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
730 *
731 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
732 * slightly longer than 5ms before the control register reports that
733 * 1.8V is ready, and far longer still before the card will actually
734 * work reliably.
735 */
736 usleep_range(100000, 110000);
737}
738
739static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
740{
741 sdhci_reset(host, mask);
742 gli_set_9750(host);
743}
744
745static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
746{
747 u32 value;
748
749 value = readl(host->ioaddr + reg);
750 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
751 value |= 0xc8;
752
753 return value;
754}
755
756#ifdef CONFIG_PM_SLEEP
757static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
758{
759 struct sdhci_pci_slot *slot = chip->slots[0];
760
761 pci_free_irq_vectors(slot->chip->pdev);
762 gli_pcie_enable_msi(slot);
763
764 return sdhci_pci_resume_host(chip);
765}
766
767static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
768{
769 struct sdhci_pci_slot *slot = chip->slots[0];
770 int ret;
771
772 ret = sdhci_pci_gli_resume(chip);
773 if (ret)
774 return ret;
775
776 return cqhci_resume(slot->host->mmc);
777}
778
779static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
780{
781 struct sdhci_pci_slot *slot = chip->slots[0];
782 int ret;
783
784 ret = cqhci_suspend(slot->host->mmc);
785 if (ret)
786 return ret;
787
788 return sdhci_suspend_host(slot->host);
789}
790#endif
791
792static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
793 struct mmc_ios *ios)
794{
795 struct sdhci_host *host = mmc_priv(mmc);
796 u32 val;
797
798 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
799 if (ios->enhanced_strobe)
800 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
801 else
802 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
803
804 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
805}
806
807static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
808 unsigned int timing)
809{
810 u16 ctrl_2;
811
812 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
813 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
814 if (timing == MMC_TIMING_MMC_HS200)
815 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
816 else if (timing == MMC_TIMING_MMC_HS)
817 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
818 else if (timing == MMC_TIMING_MMC_DDR52)
819 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
820 else if (timing == MMC_TIMING_MMC_HS400)
821 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
822
823 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
824}
825
826static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
827{
828 sdhci_dumpregs(mmc_priv(mmc));
829}
830
831static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
832{
833 struct cqhci_host *cq_host = mmc->cqe_private;
834 u32 value;
835
836 value = cqhci_readl(cq_host, CQHCI_CFG);
837 value |= CQHCI_ENABLE;
838 cqhci_writel(cq_host, value, CQHCI_CFG);
839}
840
841static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
842{
843 struct sdhci_host *host = mmc_priv(mmc);
844
845 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
846 sdhci_cqe_enable(mmc);
847}
848
849static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
850{
851 int cmd_error = 0;
852 int data_error = 0;
853
854 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
855 return intmask;
856
857 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
858
859 return 0;
860}
861
862static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
863{
864 struct sdhci_host *host = mmc_priv(mmc);
865 struct cqhci_host *cq_host = mmc->cqe_private;
866 u32 value;
867
868 value = cqhci_readl(cq_host, CQHCI_CFG);
869 value &= ~CQHCI_ENABLE;
870 cqhci_writel(cq_host, value, CQHCI_CFG);
871 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
872}
873
874static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
875 .enable = sdhci_gl9763e_cqe_enable,
876 .disable = sdhci_cqe_disable,
877 .dumpregs = sdhci_gl9763e_dumpregs,
878 .pre_enable = sdhci_gl9763e_cqe_pre_enable,
879 .post_disable = sdhci_gl9763e_cqe_post_disable,
880};
881
882static int gl9763e_add_host(struct sdhci_pci_slot *slot)
883{
884 struct device *dev = &slot->chip->pdev->dev;
885 struct sdhci_host *host = slot->host;
886 struct cqhci_host *cq_host;
887 bool dma64;
888 int ret;
889
890 ret = sdhci_setup_host(host);
891 if (ret)
892 return ret;
893
894 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
895 if (!cq_host) {
896 ret = -ENOMEM;
897 goto cleanup;
898 }
899
900 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
901 cq_host->ops = &sdhci_gl9763e_cqhci_ops;
902
903 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
904 if (dma64)
905 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
906
907 ret = cqhci_init(cq_host, host->mmc, dma64);
908 if (ret)
909 goto cleanup;
910
911 ret = __sdhci_add_host(host);
912 if (ret)
913 goto cleanup;
914
915 return 0;
916
917cleanup:
918 sdhci_cleanup_host(host);
919 return ret;
920}
921
922static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
923{
924 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
925 host->mmc->cqe_private)
926 cqhci_deactivate(host->mmc);
927 sdhci_reset(host, mask);
928}
929
930static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
931{
932 struct pci_dev *pdev = slot->chip->pdev;
933 u32 value;
934
935 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
936 value &= ~GLI_9763E_VHS_REV;
937 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
938 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
939
940 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
941 value |= GLI_9763E_SCR_AXI_REQ;
942 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
943
944 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
945 value &= ~GLI_9763E_HS400_SLOW;
946 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
947
948 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
949 value &= ~GLI_9763E_CFG2_L1DLY;
950 /* set ASPM L1 entry delay to 21us */
951 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
952 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
953
954 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
955 value &= ~GLI_9763E_HS400_RXDLY;
956 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
957 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
958
959 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
960 value &= ~GLI_9763E_VHS_REV;
961 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
962 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
963}
964
965#ifdef CONFIG_PM
966static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
967{
968 struct sdhci_pci_slot *slot = chip->slots[0];
969 struct sdhci_host *host = slot->host;
970 u16 clock;
971
972 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
973 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
974 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
975
976 return 0;
977}
978
979static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
980{
981 struct sdhci_pci_slot *slot = chip->slots[0];
982 struct sdhci_host *host = slot->host;
983 u16 clock;
984
985 if (host->mmc->ios.power_mode != MMC_POWER_ON)
986 return 0;
987
988 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
989
990 clock |= SDHCI_CLOCK_PLL_EN;
991 clock &= ~SDHCI_CLOCK_INT_STABLE;
992 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
993
994 /* Wait max 150 ms */
995 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
996 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
997 pr_err("%s: PLL clock never stabilised.\n",
998 mmc_hostname(host->mmc));
999 sdhci_dumpregs(host);
1000 }
1001
1002 clock |= SDHCI_CLOCK_CARD_EN;
1003 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1004
1005 return 0;
1006}
1007#endif
1008
1009static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
1010{
1011 struct pci_dev *pdev = slot->chip->pdev;
1012 struct sdhci_host *host = slot->host;
1013 u32 value;
1014
1015 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1016 MMC_CAP_1_8V_DDR |
1017 MMC_CAP_NONREMOVABLE;
1018 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1019 MMC_CAP2_HS400_1_8V |
1020 MMC_CAP2_HS400_ES |
1021 MMC_CAP2_NO_SDIO |
1022 MMC_CAP2_NO_SD;
1023
1024 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1025 if (!(value & GLI_9763E_MB_CMDQ_OFF))
1026 if (value & GLI_9763E_MB_ERP_ON)
1027 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1028
1029 gli_pcie_enable_msi(slot);
1030 host->mmc_host_ops.hs400_enhanced_strobe =
1031 gl9763e_hs400_enhanced_strobe;
1032 gli_set_gl9763e(slot);
1033 sdhci_enable_v4_mode(host);
1034
1035 return 0;
1036}
1037
1038#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1039
1040static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1041{
1042 u32 val = readl(host->ioaddr + (reg & ~3));
1043 u16 word;
1044
1045 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1046 return word;
1047}
1048
1049static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1050{
1051 u32 val = readl(host->ioaddr + (reg & ~3));
1052 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1053
1054 return byte;
1055}
1056
1057static const struct sdhci_ops sdhci_gl9755_ops = {
1058 .read_w = sdhci_gli_readw,
1059 .read_b = sdhci_gli_readb,
1060 .set_clock = sdhci_gl9755_set_clock,
1061 .enable_dma = sdhci_pci_enable_dma,
1062 .set_bus_width = sdhci_set_bus_width,
1063 .reset = sdhci_reset,
1064 .set_uhs_signaling = sdhci_set_uhs_signaling,
1065 .voltage_switch = sdhci_gli_voltage_switch,
1066};
1067
1068const struct sdhci_pci_fixes sdhci_gl9755 = {
1069 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1070 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1071 .probe_slot = gli_probe_slot_gl9755,
1072 .ops = &sdhci_gl9755_ops,
1073#ifdef CONFIG_PM_SLEEP
1074 .resume = sdhci_pci_gli_resume,
1075#endif
1076};
1077
1078static const struct sdhci_ops sdhci_gl9750_ops = {
1079 .read_w = sdhci_gli_readw,
1080 .read_b = sdhci_gli_readb,
1081 .read_l = sdhci_gl9750_readl,
1082 .set_clock = sdhci_gl9750_set_clock,
1083 .enable_dma = sdhci_pci_enable_dma,
1084 .set_bus_width = sdhci_set_bus_width,
1085 .reset = sdhci_gl9750_reset,
1086 .set_uhs_signaling = sdhci_set_uhs_signaling,
1087 .voltage_switch = sdhci_gli_voltage_switch,
1088 .platform_execute_tuning = gl9750_execute_tuning,
1089};
1090
1091const struct sdhci_pci_fixes sdhci_gl9750 = {
1092 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1093 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1094 .probe_slot = gli_probe_slot_gl9750,
1095 .ops = &sdhci_gl9750_ops,
1096#ifdef CONFIG_PM_SLEEP
1097 .resume = sdhci_pci_gli_resume,
1098#endif
1099};
1100
1101static const struct sdhci_ops sdhci_gl9763e_ops = {
1102 .set_clock = sdhci_set_clock,
1103 .enable_dma = sdhci_pci_enable_dma,
1104 .set_bus_width = sdhci_set_bus_width,
1105 .reset = sdhci_gl9763e_reset,
1106 .set_uhs_signaling = sdhci_set_gl9763e_signaling,
1107 .voltage_switch = sdhci_gli_voltage_switch,
1108 .irq = sdhci_gl9763e_cqhci_irq,
1109};
1110
1111const struct sdhci_pci_fixes sdhci_gl9763e = {
1112 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1113 .probe_slot = gli_probe_slot_gl9763e,
1114 .ops = &sdhci_gl9763e_ops,
1115#ifdef CONFIG_PM_SLEEP
1116 .resume = sdhci_cqhci_gli_resume,
1117 .suspend = sdhci_cqhci_gli_suspend,
1118#endif
1119#ifdef CONFIG_PM
1120 .runtime_suspend = gl9763e_runtime_suspend,
1121 .runtime_resume = gl9763e_runtime_resume,
1122 .allow_runtime_pm = true,
1123#endif
1124 .add_host = gl9763e_add_host,
1125};