tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_7.h"
26
27#include "nbio/nbio_7_7_0_offset.h"
28#include "nbio/nbio_7_7_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
32{
33 u32 tmp;
34
35 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
36 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
37 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
38
39 return tmp;
40}
41
42static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable)
43{
44 if (enable)
45 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
46 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
47 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
48 else
49 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
50}
51
52static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev)
53{
54 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
55}
56
57static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
58 bool use_doorbell, int doorbell_index,
59 int doorbell_size)
60{
61 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
62 u32 doorbell_range = RREG32_PCIE_PORT(reg);
63
64 if (use_doorbell) {
65 doorbell_range = REG_SET_FIELD(doorbell_range,
66 GDC0_BIF_SDMA0_DOORBELL_RANGE,
67 OFFSET, doorbell_index);
68 doorbell_range = REG_SET_FIELD(doorbell_range,
69 GDC0_BIF_SDMA0_DOORBELL_RANGE,
70 SIZE, doorbell_size);
71 } else {
72 doorbell_range = REG_SET_FIELD(doorbell_range,
73 GDC0_BIF_SDMA0_DOORBELL_RANGE,
74 SIZE, 0);
75 }
76
77 WREG32_PCIE_PORT(reg, doorbell_range);
78}
79
80static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev,
81 bool enable)
82{
83 u32 reg;
84
85 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
86 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
87 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
88
89 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
90}
91
92static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
93 bool enable)
94{
95 u32 tmp = 0;
96
97 if (enable) {
98 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
99 DOORBELL_SELFRING_GPA_APER_EN, 1) |
100 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
101 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
102 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
103 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
104
105 WREG32_SOC15(NBIO, 0,
106 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
107 lower_32_bits(adev->doorbell.base));
108 WREG32_SOC15(NBIO, 0,
109 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
110 upper_32_bits(adev->doorbell.base));
111 }
112
113 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
114 tmp);
115}
116
117
118static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev,
119 bool use_doorbell, int doorbell_index)
120{
121 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,
122 regGDC0_BIF_IH_DOORBELL_RANGE);
123
124 if (use_doorbell) {
125 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
126 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
127 doorbell_index);
128 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
129 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
130 2);
131 } else {
132 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
133 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
134 0);
135 }
136
137 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
138 ih_doorbell_range);
139}
140
141static void nbio_v7_7_ih_control(struct amdgpu_device *adev)
142{
143 u32 interrupt_cntl;
144
145 /* setup interrupt control */
146 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
147 adev->dummy_page_addr >> 8);
148
149 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
150 /*
151 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
152 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
153 */
154 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
155 IH_DUMMY_RD_OVERRIDE, 0);
156
157 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
158 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
159 IH_REQ_NONSNOOP_EN, 0);
160
161 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
162}
163
164static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev)
165{
166 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
167}
168
169static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev)
170{
171 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
172}
173
174static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev)
175{
176 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
177}
178
179static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev)
180{
181 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
182}
183
184static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev)
185{
186 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
187}
188
189static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev)
190{
191 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
192}
193
194const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = {
195 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
196 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
197 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
198 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
199 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
200 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
201 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
202 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
203 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
204 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
205 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
206 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
207};
208
209static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
210{
211 uint32_t def, data;
212
213 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
214 data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
215 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
216 data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
217 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
218
219 if (def != data)
220 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
221
222}
223
224const struct amdgpu_nbio_funcs nbio_v7_7_funcs = {
225 .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset,
226 .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset,
227 .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset,
228 .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset,
229 .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset,
230 .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset,
231 .get_rev_id = nbio_v7_7_get_rev_id,
232 .mc_access_enable = nbio_v7_7_mc_access_enable,
233 .get_memsize = nbio_v7_7_get_memsize,
234 .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range,
235 .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture,
236 .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture,
237 .ih_doorbell_range = nbio_v7_7_ih_doorbell_range,
238 .ih_control = nbio_v7_7_ih_control,
239 .init_registers = nbio_v7_7_init_registers,
240};