tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Seiya Wang <seiya.wang@mediatek.com>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/mt8192-clk.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/memory/mt8192-larb-port.h>
12#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/power/mt8192-power.h>
15
16/ {
17 compatible = "mediatek,mt8192";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 clk26m: oscillator0 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <26000000>;
26 clock-output-names = "clk26m";
27 };
28
29 clk32k: oscillator1 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <32768>;
33 clock-output-names = "clk32k";
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a55";
43 reg = <0x000>;
44 enable-method = "psci";
45 clock-frequency = <1701000000>;
46 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
47 next-level-cache = <&l2_0>;
48 capacity-dmips-mhz = <530>;
49 };
50
51 cpu1: cpu@100 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a55";
54 reg = <0x100>;
55 enable-method = "psci";
56 clock-frequency = <1701000000>;
57 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
58 next-level-cache = <&l2_0>;
59 capacity-dmips-mhz = <530>;
60 };
61
62 cpu2: cpu@200 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a55";
65 reg = <0x200>;
66 enable-method = "psci";
67 clock-frequency = <1701000000>;
68 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
69 next-level-cache = <&l2_0>;
70 capacity-dmips-mhz = <530>;
71 };
72
73 cpu3: cpu@300 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a55";
76 reg = <0x300>;
77 enable-method = "psci";
78 clock-frequency = <1701000000>;
79 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
80 next-level-cache = <&l2_0>;
81 capacity-dmips-mhz = <530>;
82 };
83
84 cpu4: cpu@400 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a76";
87 reg = <0x400>;
88 enable-method = "psci";
89 clock-frequency = <2171000000>;
90 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
91 next-level-cache = <&l2_1>;
92 capacity-dmips-mhz = <1024>;
93 };
94
95 cpu5: cpu@500 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a76";
98 reg = <0x500>;
99 enable-method = "psci";
100 clock-frequency = <2171000000>;
101 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
102 next-level-cache = <&l2_1>;
103 capacity-dmips-mhz = <1024>;
104 };
105
106 cpu6: cpu@600 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a76";
109 reg = <0x600>;
110 enable-method = "psci";
111 clock-frequency = <2171000000>;
112 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
113 next-level-cache = <&l2_1>;
114 capacity-dmips-mhz = <1024>;
115 };
116
117 cpu7: cpu@700 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a76";
120 reg = <0x700>;
121 enable-method = "psci";
122 clock-frequency = <2171000000>;
123 cpu-idle-states = <&cpuoff_b &clusteroff_b>;
124 next-level-cache = <&l2_1>;
125 capacity-dmips-mhz = <1024>;
126 };
127
128 cpu-map {
129 cluster0 {
130 core0 {
131 cpu = <&cpu0>;
132 };
133 core1 {
134 cpu = <&cpu1>;
135 };
136 core2 {
137 cpu = <&cpu2>;
138 };
139 core3 {
140 cpu = <&cpu3>;
141 };
142 };
143
144 cluster1 {
145 core0 {
146 cpu = <&cpu4>;
147 };
148 core1 {
149 cpu = <&cpu5>;
150 };
151 core2 {
152 cpu = <&cpu6>;
153 };
154 core3 {
155 cpu = <&cpu7>;
156 };
157 };
158 };
159
160 l2_0: l2-cache0 {
161 compatible = "cache";
162 next-level-cache = <&l3_0>;
163 };
164
165 l2_1: l2-cache1 {
166 compatible = "cache";
167 next-level-cache = <&l3_0>;
168 };
169
170 l3_0: l3-cache {
171 compatible = "cache";
172 };
173
174 idle-states {
175 entry-method = "arm,psci";
176 cpuoff_l: cpuoff_l {
177 compatible = "arm,idle-state";
178 arm,psci-suspend-param = <0x00010001>;
179 local-timer-stop;
180 entry-latency-us = <55>;
181 exit-latency-us = <140>;
182 min-residency-us = <780>;
183 };
184 cpuoff_b: cpuoff_b {
185 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x00010001>;
187 local-timer-stop;
188 entry-latency-us = <35>;
189 exit-latency-us = <145>;
190 min-residency-us = <720>;
191 };
192 clusteroff_l: clusteroff_l {
193 compatible = "arm,idle-state";
194 arm,psci-suspend-param = <0x01010002>;
195 local-timer-stop;
196 entry-latency-us = <60>;
197 exit-latency-us = <155>;
198 min-residency-us = <860>;
199 };
200 clusteroff_b: clusteroff_b {
201 compatible = "arm,idle-state";
202 arm,psci-suspend-param = <0x01010002>;
203 local-timer-stop;
204 entry-latency-us = <40>;
205 exit-latency-us = <155>;
206 min-residency-us = <780>;
207 };
208 };
209 };
210
211 pmu-a55 {
212 compatible = "arm,cortex-a55-pmu";
213 interrupt-parent = <&gic>;
214 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
215 };
216
217 pmu-a76 {
218 compatible = "arm,cortex-a76-pmu";
219 interrupt-parent = <&gic>;
220 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
221 };
222
223 psci {
224 compatible = "arm,psci-1.0";
225 method = "smc";
226 };
227
228 timer: timer {
229 compatible = "arm,armv8-timer";
230 interrupt-parent = <&gic>;
231 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
232 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
233 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
234 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
235 clock-frequency = <13000000>;
236 };
237
238 soc {
239 #address-cells = <2>;
240 #size-cells = <2>;
241 compatible = "simple-bus";
242 ranges;
243
244 gic: interrupt-controller@c000000 {
245 compatible = "arm,gic-v3";
246 #interrupt-cells = <4>;
247 #redistributor-regions = <1>;
248 interrupt-parent = <&gic>;
249 interrupt-controller;
250 reg = <0 0x0c000000 0 0x40000>,
251 <0 0x0c040000 0 0x200000>;
252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
253
254 ppi-partitions {
255 ppi_cluster0: interrupt-partition-0 {
256 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
257 };
258 ppi_cluster1: interrupt-partition-1 {
259 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
260 };
261 };
262 };
263
264 topckgen: syscon@10000000 {
265 compatible = "mediatek,mt8192-topckgen", "syscon";
266 reg = <0 0x10000000 0 0x1000>;
267 #clock-cells = <1>;
268 };
269
270 infracfg: syscon@10001000 {
271 compatible = "mediatek,mt8192-infracfg", "syscon";
272 reg = <0 0x10001000 0 0x1000>;
273 #clock-cells = <1>;
274 };
275
276 pericfg: syscon@10003000 {
277 compatible = "mediatek,mt8192-pericfg", "syscon";
278 reg = <0 0x10003000 0 0x1000>;
279 #clock-cells = <1>;
280 };
281
282 pio: pinctrl@10005000 {
283 compatible = "mediatek,mt8192-pinctrl";
284 reg = <0 0x10005000 0 0x1000>,
285 <0 0x11c20000 0 0x1000>,
286 <0 0x11d10000 0 0x1000>,
287 <0 0x11d30000 0 0x1000>,
288 <0 0x11d40000 0 0x1000>,
289 <0 0x11e20000 0 0x1000>,
290 <0 0x11e70000 0 0x1000>,
291 <0 0x11ea0000 0 0x1000>,
292 <0 0x11f20000 0 0x1000>,
293 <0 0x11f30000 0 0x1000>,
294 <0 0x1000b000 0 0x1000>;
295 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
296 "iocfg_bl", "iocfg_br", "iocfg_lm",
297 "iocfg_lb", "iocfg_rt", "iocfg_lt",
298 "iocfg_tl", "eint";
299 gpio-controller;
300 #gpio-cells = <2>;
301 gpio-ranges = <&pio 0 0 220>;
302 interrupt-controller;
303 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
304 #interrupt-cells = <2>;
305 };
306
307 scpsys: syscon@10006000 {
308 compatible = "syscon", "simple-mfd";
309 reg = <0 0x10006000 0 0x1000>;
310 #power-domain-cells = <1>;
311
312 /* System Power Manager */
313 spm: power-controller {
314 compatible = "mediatek,mt8192-power-controller";
315 #address-cells = <1>;
316 #size-cells = <0>;
317 #power-domain-cells = <1>;
318
319 /* power domain of the SoC */
320 power-domain@MT8192_POWER_DOMAIN_AUDIO {
321 reg = <MT8192_POWER_DOMAIN_AUDIO>;
322 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
323 <&infracfg CLK_INFRA_AUDIO_26M_B>,
324 <&infracfg CLK_INFRA_AUDIO>;
325 clock-names = "audio", "audio1", "audio2";
326 mediatek,infracfg = <&infracfg>;
327 #power-domain-cells = <0>;
328 };
329
330 power-domain@MT8192_POWER_DOMAIN_CONN {
331 reg = <MT8192_POWER_DOMAIN_CONN>;
332 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
333 clock-names = "conn";
334 mediatek,infracfg = <&infracfg>;
335 #power-domain-cells = <0>;
336 };
337
338 power-domain@MT8192_POWER_DOMAIN_MFG0 {
339 reg = <MT8192_POWER_DOMAIN_MFG0>;
340 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
341 clock-names = "mfg";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 #power-domain-cells = <1>;
345
346 power-domain@MT8192_POWER_DOMAIN_MFG1 {
347 reg = <MT8192_POWER_DOMAIN_MFG1>;
348 mediatek,infracfg = <&infracfg>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 #power-domain-cells = <1>;
352
353 power-domain@MT8192_POWER_DOMAIN_MFG2 {
354 reg = <MT8192_POWER_DOMAIN_MFG2>;
355 #power-domain-cells = <0>;
356 };
357
358 power-domain@MT8192_POWER_DOMAIN_MFG3 {
359 reg = <MT8192_POWER_DOMAIN_MFG3>;
360 #power-domain-cells = <0>;
361 };
362
363 power-domain@MT8192_POWER_DOMAIN_MFG4 {
364 reg = <MT8192_POWER_DOMAIN_MFG4>;
365 #power-domain-cells = <0>;
366 };
367
368 power-domain@MT8192_POWER_DOMAIN_MFG5 {
369 reg = <MT8192_POWER_DOMAIN_MFG5>;
370 #power-domain-cells = <0>;
371 };
372
373 power-domain@MT8192_POWER_DOMAIN_MFG6 {
374 reg = <MT8192_POWER_DOMAIN_MFG6>;
375 #power-domain-cells = <0>;
376 };
377 };
378 };
379
380 power-domain@MT8192_POWER_DOMAIN_DISP {
381 reg = <MT8192_POWER_DOMAIN_DISP>;
382 clocks = <&topckgen CLK_TOP_DISP_SEL>,
383 <&mmsys CLK_MM_SMI_INFRA>,
384 <&mmsys CLK_MM_SMI_COMMON>,
385 <&mmsys CLK_MM_SMI_GALS>,
386 <&mmsys CLK_MM_SMI_IOMMU>;
387 clock-names = "disp", "disp-0", "disp-1", "disp-2",
388 "disp-3";
389 mediatek,infracfg = <&infracfg>;
390 #address-cells = <1>;
391 #size-cells = <0>;
392 #power-domain-cells = <1>;
393
394 power-domain@MT8192_POWER_DOMAIN_IPE {
395 reg = <MT8192_POWER_DOMAIN_IPE>;
396 clocks = <&topckgen CLK_TOP_IPE_SEL>,
397 <&ipesys CLK_IPE_LARB19>,
398 <&ipesys CLK_IPE_LARB20>,
399 <&ipesys CLK_IPE_SMI_SUBCOM>,
400 <&ipesys CLK_IPE_GALS>;
401 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
402 "ipe-3";
403 mediatek,infracfg = <&infracfg>;
404 #power-domain-cells = <0>;
405 };
406
407 power-domain@MT8192_POWER_DOMAIN_ISP {
408 reg = <MT8192_POWER_DOMAIN_ISP>;
409 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
410 <&imgsys CLK_IMG_LARB9>,
411 <&imgsys CLK_IMG_GALS>;
412 clock-names = "isp", "isp-0", "isp-1";
413 mediatek,infracfg = <&infracfg>;
414 #power-domain-cells = <0>;
415 };
416
417 power-domain@MT8192_POWER_DOMAIN_ISP2 {
418 reg = <MT8192_POWER_DOMAIN_ISP2>;
419 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
420 <&imgsys2 CLK_IMG2_LARB11>,
421 <&imgsys2 CLK_IMG2_GALS>;
422 clock-names = "isp2", "isp2-0", "isp2-1";
423 mediatek,infracfg = <&infracfg>;
424 #power-domain-cells = <0>;
425 };
426
427 power-domain@MT8192_POWER_DOMAIN_MDP {
428 reg = <MT8192_POWER_DOMAIN_MDP>;
429 clocks = <&topckgen CLK_TOP_MDP_SEL>,
430 <&mdpsys CLK_MDP_SMI0>;
431 clock-names = "mdp", "mdp-0";
432 mediatek,infracfg = <&infracfg>;
433 #power-domain-cells = <0>;
434 };
435
436 power-domain@MT8192_POWER_DOMAIN_VENC {
437 reg = <MT8192_POWER_DOMAIN_VENC>;
438 clocks = <&topckgen CLK_TOP_VENC_SEL>,
439 <&vencsys CLK_VENC_SET1_VENC>;
440 clock-names = "venc", "venc-0";
441 mediatek,infracfg = <&infracfg>;
442 #power-domain-cells = <0>;
443 };
444
445 power-domain@MT8192_POWER_DOMAIN_VDEC {
446 reg = <MT8192_POWER_DOMAIN_VDEC>;
447 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
448 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
449 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
450 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
451 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
452 mediatek,infracfg = <&infracfg>;
453 #address-cells = <1>;
454 #size-cells = <0>;
455 #power-domain-cells = <1>;
456
457 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
458 reg = <MT8192_POWER_DOMAIN_VDEC2>;
459 clocks = <&vdecsys CLK_VDEC_VDEC>,
460 <&vdecsys CLK_VDEC_LAT>,
461 <&vdecsys CLK_VDEC_LARB1>;
462 clock-names = "vdec2-0", "vdec2-1",
463 "vdec2-2";
464 #power-domain-cells = <0>;
465 };
466 };
467
468 power-domain@MT8192_POWER_DOMAIN_CAM {
469 reg = <MT8192_POWER_DOMAIN_CAM>;
470 clocks = <&topckgen CLK_TOP_CAM_SEL>,
471 <&camsys CLK_CAM_LARB13>,
472 <&camsys CLK_CAM_LARB14>,
473 <&camsys CLK_CAM_CCU_GALS>,
474 <&camsys CLK_CAM_CAM2MM_GALS>;
475 clock-names = "cam", "cam-0", "cam-1", "cam-2",
476 "cam-3";
477 mediatek,infracfg = <&infracfg>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <1>;
481
482 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
483 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
484 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
485 clock-names = "cam_rawa-0";
486 #power-domain-cells = <0>;
487 };
488
489 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
490 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
491 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
492 clock-names = "cam_rawb-0";
493 #power-domain-cells = <0>;
494 };
495
496 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
497 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
498 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
499 clock-names = "cam_rawc-0";
500 #power-domain-cells = <0>;
501 };
502 };
503 };
504 };
505 };
506
507 watchdog: watchdog@10007000 {
508 compatible = "mediatek,mt8192-wdt";
509 reg = <0 0x10007000 0 0x100>;
510 #reset-cells = <1>;
511 };
512
513 apmixedsys: syscon@1000c000 {
514 compatible = "mediatek,mt8192-apmixedsys", "syscon";
515 reg = <0 0x1000c000 0 0x1000>;
516 #clock-cells = <1>;
517 };
518
519 systimer: timer@10017000 {
520 compatible = "mediatek,mt8192-timer",
521 "mediatek,mt6765-timer";
522 reg = <0 0x10017000 0 0x1000>;
523 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
524 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
525 clock-names = "clk13m";
526 };
527
528 pwrap: pwrap@10026000 {
529 compatible = "mediatek,mt6873-pwrap";
530 reg = <0 0x10026000 0 0x1000>;
531 reg-names = "pwrap";
532 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
533 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
534 <&infracfg CLK_INFRA_PMIC_TMR>;
535 clock-names = "spi", "wrap";
536 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
537 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
538 };
539
540 spmi: spmi@10027000 {
541 compatible = "mediatek,mt6873-spmi";
542 reg = <0 0x10027000 0 0x000e00>,
543 <0 0x10029000 0 0x000100>;
544 reg-names = "pmif", "spmimst";
545 clocks = <&infracfg CLK_INFRA_PMIC_AP>,
546 <&infracfg CLK_INFRA_PMIC_TMR>,
547 <&topckgen CLK_TOP_SPMI_MST_SEL>;
548 clock-names = "pmif_sys_ck",
549 "pmif_tmr_ck",
550 "spmimst_clk_mux";
551 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
552 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
553 };
554
555 scp_adsp: clock-controller@10720000 {
556 compatible = "mediatek,mt8192-scp_adsp";
557 reg = <0 0x10720000 0 0x1000>;
558 #clock-cells = <1>;
559 };
560
561 uart0: serial@11002000 {
562 compatible = "mediatek,mt8192-uart",
563 "mediatek,mt6577-uart";
564 reg = <0 0x11002000 0 0x1000>;
565 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
566 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
567 clock-names = "baud", "bus";
568 status = "disabled";
569 };
570
571 uart1: serial@11003000 {
572 compatible = "mediatek,mt8192-uart",
573 "mediatek,mt6577-uart";
574 reg = <0 0x11003000 0 0x1000>;
575 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
576 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
577 clock-names = "baud", "bus";
578 status = "disabled";
579 };
580
581 imp_iic_wrap_c: clock-controller@11007000 {
582 compatible = "mediatek,mt8192-imp_iic_wrap_c";
583 reg = <0 0x11007000 0 0x1000>;
584 #clock-cells = <1>;
585 };
586
587 spi0: spi@1100a000 {
588 compatible = "mediatek,mt8192-spi",
589 "mediatek,mt6765-spi";
590 #address-cells = <1>;
591 #size-cells = <0>;
592 reg = <0 0x1100a000 0 0x1000>;
593 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
594 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
595 <&topckgen CLK_TOP_SPI_SEL>,
596 <&infracfg CLK_INFRA_SPI0>;
597 clock-names = "parent-clk", "sel-clk", "spi-clk";
598 status = "disabled";
599 };
600
601 spi1: spi@11010000 {
602 compatible = "mediatek,mt8192-spi",
603 "mediatek,mt6765-spi";
604 #address-cells = <1>;
605 #size-cells = <0>;
606 reg = <0 0x11010000 0 0x1000>;
607 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
608 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
609 <&topckgen CLK_TOP_SPI_SEL>,
610 <&infracfg CLK_INFRA_SPI1>;
611 clock-names = "parent-clk", "sel-clk", "spi-clk";
612 status = "disabled";
613 };
614
615 spi2: spi@11012000 {
616 compatible = "mediatek,mt8192-spi",
617 "mediatek,mt6765-spi";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 reg = <0 0x11012000 0 0x1000>;
621 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
622 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
623 <&topckgen CLK_TOP_SPI_SEL>,
624 <&infracfg CLK_INFRA_SPI2>;
625 clock-names = "parent-clk", "sel-clk", "spi-clk";
626 status = "disabled";
627 };
628
629 spi3: spi@11013000 {
630 compatible = "mediatek,mt8192-spi",
631 "mediatek,mt6765-spi";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 reg = <0 0x11013000 0 0x1000>;
635 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
636 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
637 <&topckgen CLK_TOP_SPI_SEL>,
638 <&infracfg CLK_INFRA_SPI3>;
639 clock-names = "parent-clk", "sel-clk", "spi-clk";
640 status = "disabled";
641 };
642
643 spi4: spi@11018000 {
644 compatible = "mediatek,mt8192-spi",
645 "mediatek,mt6765-spi";
646 #address-cells = <1>;
647 #size-cells = <0>;
648 reg = <0 0x11018000 0 0x1000>;
649 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
650 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
651 <&topckgen CLK_TOP_SPI_SEL>,
652 <&infracfg CLK_INFRA_SPI4>;
653 clock-names = "parent-clk", "sel-clk", "spi-clk";
654 status = "disabled";
655 };
656
657 spi5: spi@11019000 {
658 compatible = "mediatek,mt8192-spi",
659 "mediatek,mt6765-spi";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 reg = <0 0x11019000 0 0x1000>;
663 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
664 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
665 <&topckgen CLK_TOP_SPI_SEL>,
666 <&infracfg CLK_INFRA_SPI5>;
667 clock-names = "parent-clk", "sel-clk", "spi-clk";
668 status = "disabled";
669 };
670
671 spi6: spi@1101d000 {
672 compatible = "mediatek,mt8192-spi",
673 "mediatek,mt6765-spi";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 reg = <0 0x1101d000 0 0x1000>;
677 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
678 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
679 <&topckgen CLK_TOP_SPI_SEL>,
680 <&infracfg CLK_INFRA_SPI6>;
681 clock-names = "parent-clk", "sel-clk", "spi-clk";
682 status = "disabled";
683 };
684
685 spi7: spi@1101e000 {
686 compatible = "mediatek,mt8192-spi",
687 "mediatek,mt6765-spi";
688 #address-cells = <1>;
689 #size-cells = <0>;
690 reg = <0 0x1101e000 0 0x1000>;
691 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
692 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
693 <&topckgen CLK_TOP_SPI_SEL>,
694 <&infracfg CLK_INFRA_SPI7>;
695 clock-names = "parent-clk", "sel-clk", "spi-clk";
696 status = "disabled";
697 };
698
699 scp: scp@10500000 {
700 compatible = "mediatek,mt8192-scp";
701 reg = <0 0x10500000 0 0x100000>,
702 <0 0x10720000 0 0xe0000>,
703 <0 0x10700000 0 0x8000>;
704 reg-names = "sram", "cfg", "l1tcm";
705 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
706 clocks = <&infracfg CLK_INFRA_SCPSYS>;
707 clock-names = "main";
708 status = "disabled";
709 };
710
711 xhci: usb@11200000 {
712 compatible = "mediatek,mt8192-xhci",
713 "mediatek,mtk-xhci";
714 reg = <0 0x11200000 0 0x1000>,
715 <0 0x11203e00 0 0x0100>;
716 reg-names = "mac", "ippc";
717 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
718 interrupt-names = "host";
719 phys = <&u2port0 PHY_TYPE_USB2>,
720 <&u3port0 PHY_TYPE_USB3>;
721 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
722 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
723 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
724 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
725 clocks = <&infracfg CLK_INFRA_SSUSB>,
726 <&infracfg CLK_INFRA_SSUSB_XHCI>,
727 <&apmixedsys CLK_APMIXED_USBPLL>;
728 clock-names = "sys_ck", "xhci_ck", "ref_ck";
729 wakeup-source;
730 mediatek,syscon-wakeup = <&pericfg 0x420 102>;
731 status = "disabled";
732 };
733
734 audsys: syscon@11210000 {
735 compatible = "mediatek,mt8192-audsys", "syscon";
736 reg = <0 0x11210000 0 0x2000>;
737 #clock-cells = <1>;
738
739 afe: mt8192-afe-pcm {
740 compatible = "mediatek,mt8192-audio";
741 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
742 resets = <&watchdog 17>;
743 reset-names = "audiosys";
744 mediatek,apmixedsys = <&apmixedsys>;
745 mediatek,infracfg = <&infracfg>;
746 mediatek,topckgen = <&topckgen>;
747 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
748 clocks = <&audsys CLK_AUD_AFE>,
749 <&audsys CLK_AUD_DAC>,
750 <&audsys CLK_AUD_DAC_PREDIS>,
751 <&audsys CLK_AUD_ADC>,
752 <&audsys CLK_AUD_ADDA6_ADC>,
753 <&audsys CLK_AUD_22M>,
754 <&audsys CLK_AUD_24M>,
755 <&audsys CLK_AUD_APLL_TUNER>,
756 <&audsys CLK_AUD_APLL2_TUNER>,
757 <&audsys CLK_AUD_TDM>,
758 <&audsys CLK_AUD_TML>,
759 <&audsys CLK_AUD_NLE>,
760 <&audsys CLK_AUD_DAC_HIRES>,
761 <&audsys CLK_AUD_ADC_HIRES>,
762 <&audsys CLK_AUD_ADC_HIRES_TML>,
763 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
764 <&audsys CLK_AUD_3RD_DAC>,
765 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
766 <&audsys CLK_AUD_3RD_DAC_TML>,
767 <&audsys CLK_AUD_3RD_DAC_HIRES>,
768 <&infracfg CLK_INFRA_AUDIO>,
769 <&infracfg CLK_INFRA_AUDIO_26M_B>,
770 <&topckgen CLK_TOP_AUDIO_SEL>,
771 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
772 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
773 <&topckgen CLK_TOP_AUD_1_SEL>,
774 <&topckgen CLK_TOP_APLL1>,
775 <&topckgen CLK_TOP_AUD_2_SEL>,
776 <&topckgen CLK_TOP_APLL2>,
777 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
778 <&topckgen CLK_TOP_APLL1_D4>,
779 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
780 <&topckgen CLK_TOP_APLL2_D4>,
781 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
782 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
783 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
784 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
785 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
786 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
787 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
788 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
789 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
790 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
791 <&topckgen CLK_TOP_APLL12_DIV0>,
792 <&topckgen CLK_TOP_APLL12_DIV1>,
793 <&topckgen CLK_TOP_APLL12_DIV2>,
794 <&topckgen CLK_TOP_APLL12_DIV3>,
795 <&topckgen CLK_TOP_APLL12_DIV4>,
796 <&topckgen CLK_TOP_APLL12_DIVB>,
797 <&topckgen CLK_TOP_APLL12_DIV5>,
798 <&topckgen CLK_TOP_APLL12_DIV6>,
799 <&topckgen CLK_TOP_APLL12_DIV7>,
800 <&topckgen CLK_TOP_APLL12_DIV8>,
801 <&topckgen CLK_TOP_APLL12_DIV9>,
802 <&topckgen CLK_TOP_AUDIO_H_SEL>,
803 <&clk26m>;
804 clock-names = "aud_afe_clk",
805 "aud_dac_clk",
806 "aud_dac_predis_clk",
807 "aud_adc_clk",
808 "aud_adda6_adc_clk",
809 "aud_apll22m_clk",
810 "aud_apll24m_clk",
811 "aud_apll1_tuner_clk",
812 "aud_apll2_tuner_clk",
813 "aud_tdm_clk",
814 "aud_tml_clk",
815 "aud_nle",
816 "aud_dac_hires_clk",
817 "aud_adc_hires_clk",
818 "aud_adc_hires_tml",
819 "aud_adda6_adc_hires_clk",
820 "aud_3rd_dac_clk",
821 "aud_3rd_dac_predis_clk",
822 "aud_3rd_dac_tml",
823 "aud_3rd_dac_hires_clk",
824 "aud_infra_clk",
825 "aud_infra_26m_clk",
826 "top_mux_audio",
827 "top_mux_audio_int",
828 "top_mainpll_d4_d4",
829 "top_mux_aud_1",
830 "top_apll1_ck",
831 "top_mux_aud_2",
832 "top_apll2_ck",
833 "top_mux_aud_eng1",
834 "top_apll1_d4",
835 "top_mux_aud_eng2",
836 "top_apll2_d4",
837 "top_i2s0_m_sel",
838 "top_i2s1_m_sel",
839 "top_i2s2_m_sel",
840 "top_i2s3_m_sel",
841 "top_i2s4_m_sel",
842 "top_i2s5_m_sel",
843 "top_i2s6_m_sel",
844 "top_i2s7_m_sel",
845 "top_i2s8_m_sel",
846 "top_i2s9_m_sel",
847 "top_apll12_div0",
848 "top_apll12_div1",
849 "top_apll12_div2",
850 "top_apll12_div3",
851 "top_apll12_div4",
852 "top_apll12_divb",
853 "top_apll12_div5",
854 "top_apll12_div6",
855 "top_apll12_div7",
856 "top_apll12_div8",
857 "top_apll12_div9",
858 "top_mux_audio_h",
859 "top_clk26m_clk";
860 };
861 };
862
863 pcie: pcie@11230000 {
864 compatible = "mediatek,mt8192-pcie";
865 device_type = "pci";
866 reg = <0 0x11230000 0 0x2000>;
867 reg-names = "pcie-mac";
868 #address-cells = <3>;
869 #size-cells = <2>;
870 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
871 <&infracfg CLK_INFRA_PCIE_TL_26M>,
872 <&infracfg CLK_INFRA_PCIE_TL_96M>,
873 <&infracfg CLK_INFRA_PCIE_TL_32K>,
874 <&infracfg CLK_INFRA_PCIE_PERI_26M>,
875 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
876 clock-names = "pl_250m", "tl_26m", "tl_96m",
877 "tl_32k", "peri_26m", "top_133m";
878 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
879 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
880 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
881 bus-range = <0x00 0xff>;
882 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
883 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
884 #interrupt-cells = <1>;
885 interrupt-map-mask = <0 0 0 7>;
886 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
887 <0 0 0 2 &pcie_intc0 1>,
888 <0 0 0 3 &pcie_intc0 2>,
889 <0 0 0 4 &pcie_intc0 3>;
890
891 pcie_intc0: interrupt-controller {
892 interrupt-controller;
893 #address-cells = <0>;
894 #interrupt-cells = <1>;
895 };
896 };
897
898 nor_flash: spi@11234000 {
899 compatible = "mediatek,mt8192-nor";
900 reg = <0 0x11234000 0 0xe0>;
901 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
902 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
903 <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
904 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
905 clock-names = "spi", "sf", "axi";
906 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
907 assigned-clock-parents = <&clk26m>;
908 #address-cells = <1>;
909 #size-cells = <0>;
910 status = "disabled";
911 };
912
913 efuse: efuse@11c10000 {
914 compatible = "mediatek,efuse";
915 reg = <0 0x11c10000 0 0x1000>;
916 #address-cells = <1>;
917 #size-cells = <1>;
918
919 lvts_e_data1: data1@1c0 {
920 reg = <0x1c0 0x58>;
921 };
922
923 svs_calibration: calib@580 {
924 reg = <0x580 0x68>;
925 };
926 };
927
928 i2c3: i2c@11cb0000 {
929 compatible = "mediatek,mt8192-i2c";
930 reg = <0 0x11cb0000 0 0x1000>,
931 <0 0x10217300 0 0x80>;
932 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
933 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
934 <&infracfg CLK_INFRA_AP_DMA>;
935 clock-names = "main", "dma";
936 clock-div = <1>;
937 #address-cells = <1>;
938 #size-cells = <0>;
939 status = "disabled";
940 };
941
942 imp_iic_wrap_e: clock-controller@11cb1000 {
943 compatible = "mediatek,mt8192-imp_iic_wrap_e";
944 reg = <0 0x11cb1000 0 0x1000>;
945 #clock-cells = <1>;
946 };
947
948 i2c7: i2c@11d00000 {
949 compatible = "mediatek,mt8192-i2c";
950 reg = <0 0x11d00000 0 0x1000>,
951 <0 0x10217600 0 0x180>;
952 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
953 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
954 <&infracfg CLK_INFRA_AP_DMA>;
955 clock-names = "main", "dma";
956 clock-div = <1>;
957 #address-cells = <1>;
958 #size-cells = <0>;
959 status = "disabled";
960 };
961
962 i2c8: i2c@11d01000 {
963 compatible = "mediatek,mt8192-i2c";
964 reg = <0 0x11d01000 0 0x1000>,
965 <0 0x10217780 0 0x180>;
966 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
967 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
968 <&infracfg CLK_INFRA_AP_DMA>;
969 clock-names = "main", "dma";
970 clock-div = <1>;
971 #address-cells = <1>;
972 #size-cells = <0>;
973 status = "disabled";
974 };
975
976 i2c9: i2c@11d02000 {
977 compatible = "mediatek,mt8192-i2c";
978 reg = <0 0x11d02000 0 0x1000>,
979 <0 0x10217900 0 0x180>;
980 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
981 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
982 <&infracfg CLK_INFRA_AP_DMA>;
983 clock-names = "main", "dma";
984 clock-div = <1>;
985 #address-cells = <1>;
986 #size-cells = <0>;
987 status = "disabled";
988 };
989
990 imp_iic_wrap_s: clock-controller@11d03000 {
991 compatible = "mediatek,mt8192-imp_iic_wrap_s";
992 reg = <0 0x11d03000 0 0x1000>;
993 #clock-cells = <1>;
994 };
995
996 i2c1: i2c@11d20000 {
997 compatible = "mediatek,mt8192-i2c";
998 reg = <0 0x11d20000 0 0x1000>,
999 <0 0x10217100 0 0x80>;
1000 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1001 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
1002 <&infracfg CLK_INFRA_AP_DMA>;
1003 clock-names = "main", "dma";
1004 clock-div = <1>;
1005 #address-cells = <1>;
1006 #size-cells = <0>;
1007 status = "disabled";
1008 };
1009
1010 i2c2: i2c@11d21000 {
1011 compatible = "mediatek,mt8192-i2c";
1012 reg = <0 0x11d21000 0 0x1000>,
1013 <0 0x10217180 0 0x180>;
1014 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1015 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
1016 <&infracfg CLK_INFRA_AP_DMA>;
1017 clock-names = "main", "dma";
1018 clock-div = <1>;
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 status = "disabled";
1022 };
1023
1024 i2c4: i2c@11d22000 {
1025 compatible = "mediatek,mt8192-i2c";
1026 reg = <0 0x11d22000 0 0x1000>,
1027 <0 0x10217380 0 0x180>;
1028 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1029 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
1030 <&infracfg CLK_INFRA_AP_DMA>;
1031 clock-names = "main", "dma";
1032 clock-div = <1>;
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 status = "disabled";
1036 };
1037
1038 imp_iic_wrap_ws: clock-controller@11d23000 {
1039 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1040 reg = <0 0x11d23000 0 0x1000>;
1041 #clock-cells = <1>;
1042 };
1043
1044 i2c5: i2c@11e00000 {
1045 compatible = "mediatek,mt8192-i2c";
1046 reg = <0 0x11e00000 0 0x1000>,
1047 <0 0x10217500 0 0x80>;
1048 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1049 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
1050 <&infracfg CLK_INFRA_AP_DMA>;
1051 clock-names = "main", "dma";
1052 clock-div = <1>;
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 status = "disabled";
1056 };
1057
1058 imp_iic_wrap_w: clock-controller@11e01000 {
1059 compatible = "mediatek,mt8192-imp_iic_wrap_w";
1060 reg = <0 0x11e01000 0 0x1000>;
1061 #clock-cells = <1>;
1062 };
1063
1064 u3phy0: t-phy@11e40000 {
1065 compatible = "mediatek,mt8192-tphy",
1066 "mediatek,generic-tphy-v2";
1067 #address-cells = <1>;
1068 #size-cells = <1>;
1069 ranges = <0x0 0x0 0x11e40000 0x1000>;
1070
1071 u2port0: usb-phy@0 {
1072 reg = <0x0 0x700>;
1073 clocks = <&clk26m>;
1074 clock-names = "ref";
1075 #phy-cells = <1>;
1076 };
1077
1078 u3port0: usb-phy@700 {
1079 reg = <0x700 0x900>;
1080 clocks = <&clk26m>;
1081 clock-names = "ref";
1082 #phy-cells = <1>;
1083 };
1084 };
1085
1086 i2c0: i2c@11f00000 {
1087 compatible = "mediatek,mt8192-i2c";
1088 reg = <0 0x11f00000 0 0x1000>,
1089 <0 0x10217080 0 0x80>;
1090 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1091 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1092 <&infracfg CLK_INFRA_AP_DMA>;
1093 clock-names = "main", "dma";
1094 clock-div = <1>;
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097 status = "disabled";
1098 };
1099
1100 i2c6: i2c@11f01000 {
1101 compatible = "mediatek,mt8192-i2c";
1102 reg = <0 0x11f01000 0 0x1000>,
1103 <0 0x10217580 0 0x80>;
1104 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1105 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
1106 <&infracfg CLK_INFRA_AP_DMA>;
1107 clock-names = "main", "dma";
1108 clock-div = <1>;
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 status = "disabled";
1112 };
1113
1114 imp_iic_wrap_n: clock-controller@11f02000 {
1115 compatible = "mediatek,mt8192-imp_iic_wrap_n";
1116 reg = <0 0x11f02000 0 0x1000>;
1117 #clock-cells = <1>;
1118 };
1119
1120 msdc_top: clock-controller@11f10000 {
1121 compatible = "mediatek,mt8192-msdc_top";
1122 reg = <0 0x11f10000 0 0x1000>;
1123 #clock-cells = <1>;
1124 };
1125
1126 mmc0: mmc@11f60000 {
1127 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1128 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1129 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1130 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1131 <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
1132 <&msdc_top CLK_MSDC_TOP_SRC_0P>,
1133 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1134 <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
1135 <&msdc_top CLK_MSDC_TOP_AXI>,
1136 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1137 clock-names = "source", "hclk", "source_cg", "sys_cg",
1138 "pclk_cg", "axi_cg", "ahb_cg";
1139 status = "disabled";
1140 };
1141
1142 mmc1: mmc@11f70000 {
1143 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1144 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1145 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1146 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1147 <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
1148 <&msdc_top CLK_MSDC_TOP_SRC_1P>,
1149 <&msdc_top CLK_MSDC_TOP_P_CFG>,
1150 <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
1151 <&msdc_top CLK_MSDC_TOP_AXI>,
1152 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1153 clock-names = "source", "hclk", "source_cg", "sys_cg",
1154 "pclk_cg", "axi_cg", "ahb_cg";
1155 status = "disabled";
1156 };
1157
1158 mfgcfg: clock-controller@13fbf000 {
1159 compatible = "mediatek,mt8192-mfgcfg";
1160 reg = <0 0x13fbf000 0 0x1000>;
1161 #clock-cells = <1>;
1162 };
1163
1164 mmsys: syscon@14000000 {
1165 compatible = "mediatek,mt8192-mmsys", "syscon";
1166 reg = <0 0x14000000 0 0x1000>;
1167 #clock-cells = <1>;
1168 };
1169
1170 smi_common: smi@14002000 {
1171 compatible = "mediatek,mt8192-smi-common";
1172 reg = <0 0x14002000 0 0x1000>;
1173 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1174 <&mmsys CLK_MM_SMI_INFRA>,
1175 <&mmsys CLK_MM_SMI_GALS>,
1176 <&mmsys CLK_MM_SMI_GALS>;
1177 clock-names = "apb", "smi", "gals0", "gals1";
1178 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1179 };
1180
1181 larb0: larb@14003000 {
1182 compatible = "mediatek,mt8192-smi-larb";
1183 reg = <0 0x14003000 0 0x1000>;
1184 mediatek,larb-id = <0>;
1185 mediatek,smi = <&smi_common>;
1186 clocks = <&clk26m>, <&clk26m>;
1187 clock-names = "apb", "smi";
1188 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1189 };
1190
1191 larb1: larb@14004000 {
1192 compatible = "mediatek,mt8192-smi-larb";
1193 reg = <0 0x14004000 0 0x1000>;
1194 mediatek,larb-id = <1>;
1195 mediatek,smi = <&smi_common>;
1196 clocks = <&clk26m>, <&clk26m>;
1197 clock-names = "apb", "smi";
1198 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1199 };
1200
1201 dpi0: dpi@14016000 {
1202 compatible = "mediatek,mt8192-dpi";
1203 reg = <0 0x14016000 0 0x1000>;
1204 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1205 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1206 <&mmsys CLK_MM_DISP_DPI0>,
1207 <&apmixedsys CLK_APMIXED_TVDPLL>;
1208 clock-names = "pixel", "engine", "pll";
1209 status = "disabled";
1210 };
1211
1212 iommu0: m4u@1401d000 {
1213 compatible = "mediatek,mt8192-m4u";
1214 reg = <0 0x1401d000 0 0x1000>;
1215 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
1216 <&larb4>, <&larb5>, <&larb7>,
1217 <&larb9>, <&larb11>, <&larb13>,
1218 <&larb14>, <&larb16>, <&larb17>,
1219 <&larb18>, <&larb19>, <&larb20>;
1220 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1221 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1222 clock-names = "bclk";
1223 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1224 #iommu-cells = <1>;
1225 };
1226
1227 imgsys: clock-controller@15020000 {
1228 compatible = "mediatek,mt8192-imgsys";
1229 reg = <0 0x15020000 0 0x1000>;
1230 #clock-cells = <1>;
1231 };
1232
1233 larb9: larb@1502e000 {
1234 compatible = "mediatek,mt8192-smi-larb";
1235 reg = <0 0x1502e000 0 0x1000>;
1236 mediatek,larb-id = <9>;
1237 mediatek,smi = <&smi_common>;
1238 clocks = <&imgsys CLK_IMG_LARB9>,
1239 <&imgsys CLK_IMG_LARB9>;
1240 clock-names = "apb", "smi";
1241 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1242 };
1243
1244 imgsys2: clock-controller@15820000 {
1245 compatible = "mediatek,mt8192-imgsys2";
1246 reg = <0 0x15820000 0 0x1000>;
1247 #clock-cells = <1>;
1248 };
1249
1250 larb11: larb@1582e000 {
1251 compatible = "mediatek,mt8192-smi-larb";
1252 reg = <0 0x1582e000 0 0x1000>;
1253 mediatek,larb-id = <11>;
1254 mediatek,smi = <&smi_common>;
1255 clocks = <&imgsys2 CLK_IMG2_LARB11>,
1256 <&imgsys2 CLK_IMG2_LARB11>;
1257 clock-names = "apb", "smi";
1258 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1259 };
1260
1261 larb5: larb@1600d000 {
1262 compatible = "mediatek,mt8192-smi-larb";
1263 reg = <0 0x1600d000 0 0x1000>;
1264 mediatek,larb-id = <5>;
1265 mediatek,smi = <&smi_common>;
1266 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1267 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1268 clock-names = "apb", "smi";
1269 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1270 };
1271
1272 vdecsys_soc: clock-controller@1600f000 {
1273 compatible = "mediatek,mt8192-vdecsys_soc";
1274 reg = <0 0x1600f000 0 0x1000>;
1275 #clock-cells = <1>;
1276 };
1277
1278 larb4: larb@1602e000 {
1279 compatible = "mediatek,mt8192-smi-larb";
1280 reg = <0 0x1602e000 0 0x1000>;
1281 mediatek,larb-id = <4>;
1282 mediatek,smi = <&smi_common>;
1283 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
1284 <&vdecsys CLK_VDEC_SOC_LARB1>;
1285 clock-names = "apb", "smi";
1286 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1287 };
1288
1289 vdecsys: clock-controller@1602f000 {
1290 compatible = "mediatek,mt8192-vdecsys";
1291 reg = <0 0x1602f000 0 0x1000>;
1292 #clock-cells = <1>;
1293 };
1294
1295 vencsys: clock-controller@17000000 {
1296 compatible = "mediatek,mt8192-vencsys";
1297 reg = <0 0x17000000 0 0x1000>;
1298 #clock-cells = <1>;
1299 };
1300
1301 larb7: larb@17010000 {
1302 compatible = "mediatek,mt8192-smi-larb";
1303 reg = <0 0x17010000 0 0x1000>;
1304 mediatek,larb-id = <7>;
1305 mediatek,smi = <&smi_common>;
1306 clocks = <&vencsys CLK_VENC_SET0_LARB>,
1307 <&vencsys CLK_VENC_SET1_VENC>;
1308 clock-names = "apb", "smi";
1309 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1310 };
1311
1312 vcodec_enc: vcodec@17020000 {
1313 compatible = "mediatek,mt8192-vcodec-enc";
1314 reg = <0 0x17020000 0 0x2000>;
1315 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1316 <&iommu0 M4U_PORT_L7_VENC_REC>,
1317 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1318 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1319 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1320 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1321 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1322 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1323 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1324 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1325 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1326 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1327 mediatek,scp = <&scp>;
1328 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1329 clocks = <&vencsys CLK_VENC_SET1_VENC>;
1330 clock-names = "venc-set1";
1331 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1332 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1333 };
1334
1335 camsys: clock-controller@1a000000 {
1336 compatible = "mediatek,mt8192-camsys";
1337 reg = <0 0x1a000000 0 0x1000>;
1338 #clock-cells = <1>;
1339 };
1340
1341 larb13: larb@1a001000 {
1342 compatible = "mediatek,mt8192-smi-larb";
1343 reg = <0 0x1a001000 0 0x1000>;
1344 mediatek,larb-id = <13>;
1345 mediatek,smi = <&smi_common>;
1346 clocks = <&camsys CLK_CAM_CAM>,
1347 <&camsys CLK_CAM_LARB13>;
1348 clock-names = "apb", "smi";
1349 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1350 };
1351
1352 larb14: larb@1a002000 {
1353 compatible = "mediatek,mt8192-smi-larb";
1354 reg = <0 0x1a002000 0 0x1000>;
1355 mediatek,larb-id = <14>;
1356 mediatek,smi = <&smi_common>;
1357 clocks = <&camsys CLK_CAM_CAM>,
1358 <&camsys CLK_CAM_LARB14>;
1359 clock-names = "apb", "smi";
1360 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1361 };
1362
1363 larb16: larb@1a00f000 {
1364 compatible = "mediatek,mt8192-smi-larb";
1365 reg = <0 0x1a00f000 0 0x1000>;
1366 mediatek,larb-id = <16>;
1367 mediatek,smi = <&smi_common>;
1368 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
1369 <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1370 clock-names = "apb", "smi";
1371 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1372 };
1373
1374 larb17: larb@1a010000 {
1375 compatible = "mediatek,mt8192-smi-larb";
1376 reg = <0 0x1a010000 0 0x1000>;
1377 mediatek,larb-id = <17>;
1378 mediatek,smi = <&smi_common>;
1379 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
1380 <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1381 clock-names = "apb", "smi";
1382 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1383 };
1384
1385 larb18: larb@1a011000 {
1386 compatible = "mediatek,mt8192-smi-larb";
1387 reg = <0 0x1a011000 0 0x1000>;
1388 mediatek,larb-id = <18>;
1389 mediatek,smi = <&smi_common>;
1390 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
1391 <&camsys_rawc CLK_CAM_RAWC_CAM>;
1392 clock-names = "apb", "smi";
1393 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1394 };
1395
1396 camsys_rawa: clock-controller@1a04f000 {
1397 compatible = "mediatek,mt8192-camsys_rawa";
1398 reg = <0 0x1a04f000 0 0x1000>;
1399 #clock-cells = <1>;
1400 };
1401
1402 camsys_rawb: clock-controller@1a06f000 {
1403 compatible = "mediatek,mt8192-camsys_rawb";
1404 reg = <0 0x1a06f000 0 0x1000>;
1405 #clock-cells = <1>;
1406 };
1407
1408 camsys_rawc: clock-controller@1a08f000 {
1409 compatible = "mediatek,mt8192-camsys_rawc";
1410 reg = <0 0x1a08f000 0 0x1000>;
1411 #clock-cells = <1>;
1412 };
1413
1414 ipesys: clock-controller@1b000000 {
1415 compatible = "mediatek,mt8192-ipesys";
1416 reg = <0 0x1b000000 0 0x1000>;
1417 #clock-cells = <1>;
1418 };
1419
1420 larb20: larb@1b00f000 {
1421 compatible = "mediatek,mt8192-smi-larb";
1422 reg = <0 0x1b00f000 0 0x1000>;
1423 mediatek,larb-id = <20>;
1424 mediatek,smi = <&smi_common>;
1425 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1426 <&ipesys CLK_IPE_LARB20>;
1427 clock-names = "apb", "smi";
1428 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1429 };
1430
1431 larb19: larb@1b10f000 {
1432 compatible = "mediatek,mt8192-smi-larb";
1433 reg = <0 0x1b10f000 0 0x1000>;
1434 mediatek,larb-id = <19>;
1435 mediatek,smi = <&smi_common>;
1436 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1437 <&ipesys CLK_IPE_LARB19>;
1438 clock-names = "apb", "smi";
1439 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1440 };
1441
1442 mdpsys: clock-controller@1f000000 {
1443 compatible = "mediatek,mt8192-mdpsys";
1444 reg = <0 0x1f000000 0 0x1000>;
1445 #clock-cells = <1>;
1446 };
1447
1448 larb2: larb@1f002000 {
1449 compatible = "mediatek,mt8192-smi-larb";
1450 reg = <0 0x1f002000 0 0x1000>;
1451 mediatek,larb-id = <2>;
1452 mediatek,smi = <&smi_common>;
1453 clocks = <&mdpsys CLK_MDP_SMI0>,
1454 <&mdpsys CLK_MDP_SMI0>;
1455 clock-names = "apb", "smi";
1456 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1457 };
1458 };
1459};