tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
8
9description: |
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster
11 data transfers between memory to memory, memory to device and device to
12 memory.
13
14maintainers:
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
17
18allOf:
19 - $ref: "dma-controller.yaml#"
20
21properties:
22 compatible:
23 oneOf:
24 - const: nvidia,tegra186-gpcdma
25 - items:
26 - const: nvidia,tegra194-gpcdma
27 - const: nvidia,tegra186-gpcdma
28
29 "#dma-cells":
30 const: 1
31
32 reg:
33 maxItems: 1
34
35 interrupts:
36 description:
37 Should contain all of the per-channel DMA interrupts in
38 ascending order with respect to the DMA channel index.
39 minItems: 1
40 maxItems: 31
41
42 resets:
43 maxItems: 1
44
45 reset-names:
46 const: gpcdma
47
48 iommus:
49 maxItems: 1
50
51 dma-coherent: true
52
53required:
54 - compatible
55 - reg
56 - interrupts
57 - resets
58 - reset-names
59 - "#dma-cells"
60 - iommus
61
62additionalProperties: false
63
64examples:
65 - |
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 #include <dt-bindings/memory/tegra186-mc.h>
68 #include <dt-bindings/reset/tegra186-reset.h>
69
70 dma-controller@2600000 {
71 compatible = "nvidia,tegra186-gpcdma";
72 reg = <0x2600000 0x210000>;
73 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
74 reset-names = "gpcdma";
75 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
106 #dma-cells = <1>;
107 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
108 dma-coherent;
109 };
110...