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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
16
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19 https://www.devicetree.org/specifications/
20
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23 ================================
24 Convention used in this document
25 ================================
26
27 This document follows the conventions described in the Devicetree
28 Specification, with the addition:
29
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
32
33 =====================================
34 cpus and cpu node bindings definition
35 =====================================
36
37 The ARM architecture, in accordance with the Devicetree Specification,
38 requires the cpus and cpu nodes to be present and contain the properties
39 described below.
40
41properties:
42 reg:
43 maxItems: 1
44 description: |
45 Usage and definition depend on ARM architecture version and
46 configuration:
47
48 On uniprocessor ARM architectures previous to v7
49 this property is required and must be set to 0.
50
51 On ARM 11 MPcore based systems this property is
52 required and matches the CPUID[11:0] register bits.
53
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
56
57 All other bits in the reg cell must be set to 0.
58
59 On 32-bit ARM v7 or later systems this property is
60 required and matches the CPU MPIDR[23:0] register
61 bits.
62
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
65
66 All other bits in the reg cell must be set to 0.
67
68 On ARM v8 64-bit systems this property is required
69 and matches the MPIDR_EL1 register affinity bits.
70
71 * If cpus node's #address-cells property is set to 2
72
73 The first reg cell bits [7:0] must be set to
74 bits [39:32] of MPIDR_EL1.
75
76 The second reg cell bits [23:0] must be set to
77 bits [23:0] of MPIDR_EL1.
78
79 * If cpus node's #address-cells property is set to 1
80
81 The reg cell bits [23:0] must be set to bits [23:0]
82 of MPIDR_EL1.
83
84 All other bits in the reg cells must be set to 0.
85
86 compatible:
87 enum:
88 - apple,icestorm
89 - apple,firestorm
90 - arm,arm710t
91 - arm,arm720t
92 - arm,arm740t
93 - arm,arm7ej-s
94 - arm,arm7tdmi
95 - arm,arm7tdmi-s
96 - arm,arm9es
97 - arm,arm9ej-s
98 - arm,arm920t
99 - arm,arm922t
100 - arm,arm925
101 - arm,arm926e-s
102 - arm,arm926ej-s
103 - arm,arm940t
104 - arm,arm946e-s
105 - arm,arm966e-s
106 - arm,arm968e-s
107 - arm,arm9tdmi
108 - arm,arm1020e
109 - arm,arm1020t
110 - arm,arm1022e
111 - arm,arm1026ej-s
112 - arm,arm1136j-s
113 - arm,arm1136jf-s
114 - arm,arm1156t2-s
115 - arm,arm1156t2f-s
116 - arm,arm1176jzf
117 - arm,arm1176jz-s
118 - arm,arm1176jzf-s
119 - arm,arm11mpcore
120 - arm,armv8 # Only for s/w models
121 - arm,cortex-a5
122 - arm,cortex-a7
123 - arm,cortex-a8
124 - arm,cortex-a9
125 - arm,cortex-a12
126 - arm,cortex-a15
127 - arm,cortex-a17
128 - arm,cortex-a32
129 - arm,cortex-a34
130 - arm,cortex-a35
131 - arm,cortex-a53
132 - arm,cortex-a55
133 - arm,cortex-a57
134 - arm,cortex-a65
135 - arm,cortex-a72
136 - arm,cortex-a73
137 - arm,cortex-a75
138 - arm,cortex-a76
139 - arm,cortex-a77
140 - arm,cortex-a78
141 - arm,cortex-a510
142 - arm,cortex-a710
143 - arm,cortex-m0
144 - arm,cortex-m0+
145 - arm,cortex-m1
146 - arm,cortex-m3
147 - arm,cortex-m4
148 - arm,cortex-r4
149 - arm,cortex-r5
150 - arm,cortex-r7
151 - arm,cortex-x1
152 - arm,cortex-x2
153 - arm,neoverse-e1
154 - arm,neoverse-n1
155 - arm,neoverse-n2
156 - arm,neoverse-v1
157 - brcm,brahma-b15
158 - brcm,brahma-b53
159 - brcm,vulcan
160 - cavium,thunder
161 - cavium,thunder2
162 - faraday,fa526
163 - intel,sa110
164 - intel,sa1100
165 - marvell,feroceon
166 - marvell,mohawk
167 - marvell,pj4a
168 - marvell,pj4b
169 - marvell,sheeva-v5
170 - marvell,sheeva-v7
171 - nvidia,tegra132-denver
172 - nvidia,tegra186-denver
173 - nvidia,tegra194-carmel
174 - qcom,krait
175 - qcom,kryo
176 - qcom,kryo250
177 - qcom,kryo260
178 - qcom,kryo280
179 - qcom,kryo385
180 - qcom,kryo468
181 - qcom,kryo485
182 - qcom,kryo560
183 - qcom,kryo570
184 - qcom,kryo685
185 - qcom,kryo780
186 - qcom,scorpion
187
188 enable-method:
189 $ref: '/schemas/types.yaml#/definitions/string'
190 oneOf:
191 # On ARM v8 64-bit this property is required
192 - enum:
193 - psci
194 - spin-table
195 # On ARM 32-bit systems this property is optional
196 - enum:
197 - actions,s500-smp
198 - allwinner,sun6i-a31
199 - allwinner,sun8i-a23
200 - allwinner,sun9i-a80-smp
201 - allwinner,sun8i-a83t-smp
202 - amlogic,meson8-smp
203 - amlogic,meson8b-smp
204 - arm,realview-smp
205 - aspeed,ast2600-smp
206 - brcm,bcm11351-cpu-method
207 - brcm,bcm23550
208 - brcm,bcm2836-smp
209 - brcm,bcm63138
210 - brcm,bcm-nsp-smp
211 - brcm,brahma-b15
212 - marvell,armada-375-smp
213 - marvell,armada-380-smp
214 - marvell,armada-390-smp
215 - marvell,armada-xp-smp
216 - marvell,98dx3236-smp
217 - marvell,mmp3-smp
218 - mediatek,mt6589-smp
219 - mediatek,mt81xx-tz-smp
220 - qcom,gcc-msm8660
221 - qcom,kpss-acc-v1
222 - qcom,kpss-acc-v2
223 - qcom,msm8226-smp
224 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
225 - qcom,msm8916-smp
226 - renesas,apmu
227 - renesas,r9a06g032-smp
228 - rockchip,rk3036-smp
229 - rockchip,rk3066-smp
230 - socionext,milbeaut-m10v-smp
231 - ste,dbx500-smp
232 - ti,am3352
233 - ti,am4372
234
235 cpu-release-addr:
236 oneOf:
237 - $ref: '/schemas/types.yaml#/definitions/uint32'
238 - $ref: '/schemas/types.yaml#/definitions/uint64'
239 description:
240 The DT specification defines this as 64-bit always, but some 32-bit Arm
241 systems have used a 32-bit value which must be supported.
242 Required for systems that have an "enable-method"
243 property value of "spin-table".
244
245 cpu-idle-states:
246 $ref: '/schemas/types.yaml#/definitions/phandle-array'
247 items:
248 maxItems: 1
249 description: |
250 List of phandles to idle state nodes supported
251 by this cpu (see ./idle-states.yaml).
252
253 capacity-dmips-mhz:
254 description:
255 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
256 DMIPS/MHz, relative to highest capacity-dmips-mhz
257 in the system.
258
259 cci-control-port: true
260
261 dynamic-power-coefficient:
262 $ref: '/schemas/types.yaml#/definitions/uint32'
263 description:
264 A u32 value that represents the running time dynamic
265 power coefficient in units of uW/MHz/V^2. The
266 coefficient can either be calculated from power
267 measurements or derived by analysis.
268
269 The dynamic power consumption of the CPU is
270 proportional to the square of the Voltage (V) and
271 the clock frequency (f). The coefficient is used to
272 calculate the dynamic power as below -
273
274 Pdyn = dynamic-power-coefficient * V^2 * f
275
276 where voltage is in V, frequency is in MHz.
277
278 performance-domains:
279 maxItems: 1
280 description:
281 List of phandles and performance domain specifiers, as defined by
282 bindings of the performance domain provider. See also
283 dvfs/performance-domain.yaml.
284
285 power-domains:
286 description:
287 List of phandles and PM domain specifiers, as defined by bindings of the
288 PM domain provider (see also ../power_domain.txt).
289
290 power-domain-names:
291 description:
292 A list of power domain name strings sorted in the same order as the
293 power-domains property.
294
295 For PSCI based platforms, the name corresponding to the index of the PSCI
296 PM domain provider, must be "psci".
297
298 qcom,saw:
299 $ref: '/schemas/types.yaml#/definitions/phandle'
300 description: |
301 Specifies the SAW* node associated with this CPU.
302
303 Required for systems that have an "enable-method" property
304 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
305
306 * arm/msm/qcom,saw2.txt
307
308 qcom,acc:
309 $ref: '/schemas/types.yaml#/definitions/phandle'
310 description: |
311 Specifies the ACC* node associated with this CPU.
312
313 Required for systems that have an "enable-method" property
314 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
315 "qcom,msm8916-smp".
316
317 * arm/msm/qcom,kpss-acc.txt
318
319 rockchip,pmu:
320 $ref: '/schemas/types.yaml#/definitions/phandle'
321 description: |
322 Specifies the syscon node controlling the cpu core power domains.
323
324 Optional for systems that have an "enable-method"
325 property value of "rockchip,rk3066-smp"
326 While optional, it is the preferred way to get access to
327 the cpu-core power-domains.
328
329 secondary-boot-reg:
330 $ref: '/schemas/types.yaml#/definitions/uint32'
331 description: |
332 Required for systems that have an "enable-method" property value of
333 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
334
335 This includes the following SoCs: |
336 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
337 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
338
339 The secondary-boot-reg property is a u32 value that specifies the
340 physical address of the register used to request the ROM holding pen
341 code release a secondary CPU. The value written to the register is
342 formed by encoding the target CPU id into the low bits of the
343 physical start address it should jump to.
344
345if:
346 # If the enable-method property contains one of those values
347 properties:
348 enable-method:
349 contains:
350 enum:
351 - brcm,bcm11351-cpu-method
352 - brcm,bcm23550
353 - brcm,bcm-nsp-smp
354 # and if enable-method is present
355 required:
356 - enable-method
357
358then:
359 required:
360 - secondary-boot-reg
361
362required:
363 - device_type
364 - reg
365 - compatible
366
367dependencies:
368 rockchip,pmu: [enable-method]
369
370additionalProperties: true
371
372examples:
373 - |
374 cpus {
375 #size-cells = <0>;
376 #address-cells = <1>;
377
378 cpu@0 {
379 device_type = "cpu";
380 compatible = "arm,cortex-a15";
381 reg = <0x0>;
382 };
383
384 cpu@1 {
385 device_type = "cpu";
386 compatible = "arm,cortex-a15";
387 reg = <0x1>;
388 };
389
390 cpu@100 {
391 device_type = "cpu";
392 compatible = "arm,cortex-a7";
393 reg = <0x100>;
394 };
395
396 cpu@101 {
397 device_type = "cpu";
398 compatible = "arm,cortex-a7";
399 reg = <0x101>;
400 };
401 };
402
403 - |
404 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
405 cpus {
406 #size-cells = <0>;
407 #address-cells = <1>;
408
409 cpu@0 {
410 device_type = "cpu";
411 compatible = "arm,cortex-a8";
412 reg = <0x0>;
413 };
414 };
415
416 - |
417 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
418 cpus {
419 #size-cells = <0>;
420 #address-cells = <1>;
421
422 cpu@0 {
423 device_type = "cpu";
424 compatible = "arm,arm926ej-s";
425 reg = <0x0>;
426 };
427 };
428
429 - |
430 // Example 4 (ARM Cortex-A57 64-bit system):
431 cpus {
432 #size-cells = <0>;
433 #address-cells = <2>;
434
435 cpu@0 {
436 device_type = "cpu";
437 compatible = "arm,cortex-a57";
438 reg = <0x0 0x0>;
439 enable-method = "spin-table";
440 cpu-release-addr = <0 0x20000000>;
441 };
442
443 cpu@1 {
444 device_type = "cpu";
445 compatible = "arm,cortex-a57";
446 reg = <0x0 0x1>;
447 enable-method = "spin-table";
448 cpu-release-addr = <0 0x20000000>;
449 };
450
451 cpu@100 {
452 device_type = "cpu";
453 compatible = "arm,cortex-a57";
454 reg = <0x0 0x100>;
455 enable-method = "spin-table";
456 cpu-release-addr = <0 0x20000000>;
457 };
458
459 cpu@101 {
460 device_type = "cpu";
461 compatible = "arm,cortex-a57";
462 reg = <0x0 0x101>;
463 enable-method = "spin-table";
464 cpu-release-addr = <0 0x20000000>;
465 };
466
467 cpu@10000 {
468 device_type = "cpu";
469 compatible = "arm,cortex-a57";
470 reg = <0x0 0x10000>;
471 enable-method = "spin-table";
472 cpu-release-addr = <0 0x20000000>;
473 };
474
475 cpu@10001 {
476 device_type = "cpu";
477 compatible = "arm,cortex-a57";
478 reg = <0x0 0x10001>;
479 enable-method = "spin-table";
480 cpu-release-addr = <0 0x20000000>;
481 };
482
483 cpu@10100 {
484 device_type = "cpu";
485 compatible = "arm,cortex-a57";
486 reg = <0x0 0x10100>;
487 enable-method = "spin-table";
488 cpu-release-addr = <0 0x20000000>;
489 };
490
491 cpu@10101 {
492 device_type = "cpu";
493 compatible = "arm,cortex-a57";
494 reg = <0x0 0x10101>;
495 enable-method = "spin-table";
496 cpu-release-addr = <0 0x20000000>;
497 };
498
499 cpu@100000000 {
500 device_type = "cpu";
501 compatible = "arm,cortex-a57";
502 reg = <0x1 0x0>;
503 enable-method = "spin-table";
504 cpu-release-addr = <0 0x20000000>;
505 };
506
507 cpu@100000001 {
508 device_type = "cpu";
509 compatible = "arm,cortex-a57";
510 reg = <0x1 0x1>;
511 enable-method = "spin-table";
512 cpu-release-addr = <0 0x20000000>;
513 };
514
515 cpu@100000100 {
516 device_type = "cpu";
517 compatible = "arm,cortex-a57";
518 reg = <0x1 0x100>;
519 enable-method = "spin-table";
520 cpu-release-addr = <0 0x20000000>;
521 };
522
523 cpu@100000101 {
524 device_type = "cpu";
525 compatible = "arm,cortex-a57";
526 reg = <0x1 0x101>;
527 enable-method = "spin-table";
528 cpu-release-addr = <0 0x20000000>;
529 };
530
531 cpu@100010000 {
532 device_type = "cpu";
533 compatible = "arm,cortex-a57";
534 reg = <0x1 0x10000>;
535 enable-method = "spin-table";
536 cpu-release-addr = <0 0x20000000>;
537 };
538
539 cpu@100010001 {
540 device_type = "cpu";
541 compatible = "arm,cortex-a57";
542 reg = <0x1 0x10001>;
543 enable-method = "spin-table";
544 cpu-release-addr = <0 0x20000000>;
545 };
546
547 cpu@100010100 {
548 device_type = "cpu";
549 compatible = "arm,cortex-a57";
550 reg = <0x1 0x10100>;
551 enable-method = "spin-table";
552 cpu-release-addr = <0 0x20000000>;
553 };
554
555 cpu@100010101 {
556 device_type = "cpu";
557 compatible = "arm,cortex-a57";
558 reg = <0x1 0x10101>;
559 enable-method = "spin-table";
560 cpu-release-addr = <0 0x20000000>;
561 };
562 };
563...