tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
12#include <dt-bindings/interconnect/qcom,sc7180.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sc7180.h"
17
18DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
19DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
20DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
21DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
22DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
23DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
24DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
25DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
26DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
27DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
28DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
29DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
30DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
31DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
32DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
33DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
34DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
35DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
36DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
37 SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
38DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
39SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
40DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
41DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
42DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
43DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
44DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
45DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
46DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
47DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
48DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
49DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
50DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
51DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
52DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
53DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
54DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
55DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
56DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
57DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
58DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
59DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
60DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
61DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
62DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
63DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
64DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
65DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
66DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
67DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
68DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
69DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
70DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
71DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
72DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
73DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
74DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
75DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
76DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
77DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
78DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
79DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
80DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
81DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
82DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
83DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
84DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
85DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
86DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
87DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
88DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
89DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
90DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
91DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
92DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
93DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
94DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
95DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
96DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
97DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
98DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
99DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
100DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
101DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
102DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
103DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
104DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
105DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
106DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
107DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
108DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
109DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
110DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
111DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
112DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
113DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
114DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
115DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
116DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
117DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
118DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
119DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
120DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
121DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
122DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
123DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
124DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
125DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
126DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
127DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
128DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
129DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
130DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
131DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
132DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
133DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
134DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
135DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
136DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
137DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
138DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
139DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
140DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
141DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
142DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
143DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
144DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
145DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
146DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
147DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
148DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
149DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
150DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
151DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
152DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
153DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
154DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
155
156DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
157DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
158DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
159DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
160DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
161DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
162DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
163DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
164DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
165DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
166DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
167DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
168DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
169DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
170DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
171DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
172DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
173DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
174DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
175DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
176DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
177DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
178DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
179DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
180
181static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
182 &bcm_cn1,
183};
184
185static struct qcom_icc_node * const aggre1_noc_nodes[] = {
186 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
187 [MASTER_QSPI] = &qhm_qspi,
188 [MASTER_QUP_0] = &qhm_qup_0,
189 [MASTER_SDCC_2] = &xm_sdc2,
190 [MASTER_EMMC] = &xm_emmc,
191 [MASTER_UFS_MEM] = &xm_ufs_mem,
192 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
193 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
194};
195
196static const struct qcom_icc_desc sc7180_aggre1_noc = {
197 .nodes = aggre1_noc_nodes,
198 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
199 .bcms = aggre1_noc_bcms,
200 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
201};
202
203static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
204 &bcm_ce0,
205};
206
207static struct qcom_icc_node * const aggre2_noc_nodes[] = {
208 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
209 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
210 [MASTER_QUP_1] = &qhm_qup_1,
211 [MASTER_USB3] = &qhm_usb3,
212 [MASTER_CRYPTO] = &qxm_crypto,
213 [MASTER_IPA] = &qxm_ipa,
214 [MASTER_QDSS_ETR] = &xm_qdss_etr,
215 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
216 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
217};
218
219static const struct qcom_icc_desc sc7180_aggre2_noc = {
220 .nodes = aggre2_noc_nodes,
221 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
222 .bcms = aggre2_noc_bcms,
223 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
224};
225
226static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
227 &bcm_mm1,
228};
229
230static struct qcom_icc_node * const camnoc_virt_nodes[] = {
231 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
232 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
233 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
234 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
235};
236
237static const struct qcom_icc_desc sc7180_camnoc_virt = {
238 .nodes = camnoc_virt_nodes,
239 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
240 .bcms = camnoc_virt_bcms,
241 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
242};
243
244static struct qcom_icc_bcm * const compute_noc_bcms[] = {
245 &bcm_co0,
246 &bcm_co2,
247 &bcm_co3,
248};
249
250static struct qcom_icc_node * const compute_noc_nodes[] = {
251 [MASTER_NPU] = &qnm_npu,
252 [MASTER_NPU_PROC] = &qxm_npu_dsp,
253 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
254};
255
256static const struct qcom_icc_desc sc7180_compute_noc = {
257 .nodes = compute_noc_nodes,
258 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
259 .bcms = compute_noc_bcms,
260 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
261};
262
263static struct qcom_icc_bcm * const config_noc_bcms[] = {
264 &bcm_cn0,
265 &bcm_cn1,
266};
267
268static struct qcom_icc_node * const config_noc_nodes[] = {
269 [MASTER_SNOC_CNOC] = &qnm_snoc,
270 [MASTER_QDSS_DAP] = &xm_qdss_dap,
271 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
272 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
273 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
274 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
275 [SLAVE_AOP] = &qhs_aop,
276 [SLAVE_AOSS] = &qhs_aoss,
277 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
278 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
279 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
280 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
281 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
282 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
283 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
284 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
285 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
286 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
287 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
288 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
289 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
290 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
291 [SLAVE_GLM] = &qhs_glm,
292 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
293 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
294 [SLAVE_IPA_CFG] = &qhs_ipa,
295 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
296 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
297 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
298 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
299 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
300 [SLAVE_PDM] = &qhs_pdm,
301 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
302 [SLAVE_PRNG] = &qhs_prng,
303 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
304 [SLAVE_QM_CFG] = &qhs_qm_cfg,
305 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
306 [SLAVE_QSPI_0] = &qhs_qspi,
307 [SLAVE_QUP_0] = &qhs_qup0,
308 [SLAVE_QUP_1] = &qhs_qup1,
309 [SLAVE_SDCC_2] = &qhs_sdc2,
310 [SLAVE_SECURITY] = &qhs_security,
311 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
312 [SLAVE_TCSR] = &qhs_tcsr,
313 [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
314 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
315 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
316 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
317 [SLAVE_USB3] = &qhs_usb3,
318 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
319 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
320 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
321 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
322};
323
324static const struct qcom_icc_desc sc7180_config_noc = {
325 .nodes = config_noc_nodes,
326 .num_nodes = ARRAY_SIZE(config_noc_nodes),
327 .bcms = config_noc_bcms,
328 .num_bcms = ARRAY_SIZE(config_noc_bcms),
329};
330
331static struct qcom_icc_node * const dc_noc_nodes[] = {
332 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
333 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
334 [SLAVE_LLCC_CFG] = &qhs_llcc,
335};
336
337static const struct qcom_icc_desc sc7180_dc_noc = {
338 .nodes = dc_noc_nodes,
339 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
340};
341
342static struct qcom_icc_bcm * const gem_noc_bcms[] = {
343 &bcm_sh0,
344 &bcm_sh2,
345 &bcm_sh3,
346 &bcm_sh4,
347};
348
349static struct qcom_icc_node * const gem_noc_nodes[] = {
350 [MASTER_APPSS_PROC] = &acm_apps0,
351 [MASTER_SYS_TCU] = &acm_sys_tcu,
352 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
353 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
354 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
355 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
356 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
357 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
358 [MASTER_GFX3D] = &qxm_gpu,
359 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
360 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
361 [SLAVE_LLCC] = &qns_llcc,
362 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
363};
364
365static const struct qcom_icc_desc sc7180_gem_noc = {
366 .nodes = gem_noc_nodes,
367 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
368 .bcms = gem_noc_bcms,
369 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
370};
371
372static struct qcom_icc_bcm *mc_virt_bcms[] = {
373 &bcm_acv,
374 &bcm_mc0,
375};
376
377static struct qcom_icc_node * const mc_virt_nodes[] = {
378 [MASTER_LLCC] = &llcc_mc,
379 [SLAVE_EBI1] = &ebi,
380};
381
382static const struct qcom_icc_desc sc7180_mc_virt = {
383 .nodes = mc_virt_nodes,
384 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
385 .bcms = mc_virt_bcms,
386 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
387};
388
389static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
390 &bcm_mm0,
391 &bcm_mm1,
392 &bcm_mm2,
393};
394
395static struct qcom_icc_node * const mmss_noc_nodes[] = {
396 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
397 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
398 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
399 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
400 [MASTER_MDP0] = &qxm_mdp0,
401 [MASTER_ROTATOR] = &qxm_rot,
402 [MASTER_VIDEO_P0] = &qxm_venus0,
403 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
404 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
405 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
406 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
407};
408
409static const struct qcom_icc_desc sc7180_mmss_noc = {
410 .nodes = mmss_noc_nodes,
411 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
412 .bcms = mmss_noc_bcms,
413 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
414};
415
416static struct qcom_icc_node * const npu_noc_nodes[] = {
417 [MASTER_NPU_SYS] = &amm_npu_sys,
418 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
419 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
420 [SLAVE_NPU_CP] = &qhs_cp,
421 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
422 [SLAVE_NPU_DPM] = &qhs_dpm,
423 [SLAVE_ISENSE_CFG] = &qhs_isense,
424 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
425 [SLAVE_NPU_TCM] = &qhs_tcm,
426 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
427 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
428};
429
430static const struct qcom_icc_desc sc7180_npu_noc = {
431 .nodes = npu_noc_nodes,
432 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
433};
434
435static struct qcom_icc_bcm * const qup_virt_bcms[] = {
436 &bcm_qup0,
437};
438
439static struct qcom_icc_node * const qup_virt_nodes[] = {
440 [MASTER_QUP_CORE_0] = &qup_core_master_1,
441 [MASTER_QUP_CORE_1] = &qup_core_master_2,
442 [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
443 [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
444};
445
446static const struct qcom_icc_desc sc7180_qup_virt = {
447 .nodes = qup_virt_nodes,
448 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
449 .bcms = qup_virt_bcms,
450 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
451};
452
453static struct qcom_icc_bcm * const system_noc_bcms[] = {
454 &bcm_sn0,
455 &bcm_sn1,
456 &bcm_sn2,
457 &bcm_sn3,
458 &bcm_sn4,
459 &bcm_sn7,
460 &bcm_sn9,
461 &bcm_sn12,
462};
463
464static struct qcom_icc_node * const system_noc_nodes[] = {
465 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
466 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
467 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
468 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
469 [MASTER_PIMEM] = &qxm_pimem,
470 [SLAVE_APPSS] = &qhs_apss,
471 [SLAVE_SNOC_CNOC] = &qns_cnoc,
472 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
473 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
474 [SLAVE_IMEM] = &qxs_imem,
475 [SLAVE_PIMEM] = &qxs_pimem,
476 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
477 [SLAVE_QDSS_STM] = &xs_qdss_stm,
478 [SLAVE_TCU] = &xs_sys_tcu_cfg,
479};
480
481static const struct qcom_icc_desc sc7180_system_noc = {
482 .nodes = system_noc_nodes,
483 .num_nodes = ARRAY_SIZE(system_noc_nodes),
484 .bcms = system_noc_bcms,
485 .num_bcms = ARRAY_SIZE(system_noc_bcms),
486};
487
488static const struct of_device_id qnoc_of_match[] = {
489 { .compatible = "qcom,sc7180-aggre1-noc",
490 .data = &sc7180_aggre1_noc},
491 { .compatible = "qcom,sc7180-aggre2-noc",
492 .data = &sc7180_aggre2_noc},
493 { .compatible = "qcom,sc7180-camnoc-virt",
494 .data = &sc7180_camnoc_virt},
495 { .compatible = "qcom,sc7180-compute-noc",
496 .data = &sc7180_compute_noc},
497 { .compatible = "qcom,sc7180-config-noc",
498 .data = &sc7180_config_noc},
499 { .compatible = "qcom,sc7180-dc-noc",
500 .data = &sc7180_dc_noc},
501 { .compatible = "qcom,sc7180-gem-noc",
502 .data = &sc7180_gem_noc},
503 { .compatible = "qcom,sc7180-mc-virt",
504 .data = &sc7180_mc_virt},
505 { .compatible = "qcom,sc7180-mmss-noc",
506 .data = &sc7180_mmss_noc},
507 { .compatible = "qcom,sc7180-npu-noc",
508 .data = &sc7180_npu_noc},
509 { .compatible = "qcom,sc7180-qup-virt",
510 .data = &sc7180_qup_virt},
511 { .compatible = "qcom,sc7180-system-noc",
512 .data = &sc7180_system_noc},
513 { }
514};
515MODULE_DEVICE_TABLE(of, qnoc_of_match);
516
517static struct platform_driver qnoc_driver = {
518 .probe = qcom_icc_rpmh_probe,
519 .remove = qcom_icc_rpmh_remove,
520 .driver = {
521 .name = "qnoc-sc7180",
522 .of_match_table = qnoc_of_match,
523 .sync_state = icc_sync_state,
524 },
525};
526module_platform_driver(qnoc_driver);
527
528MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
529MODULE_LICENSE("GPL v2");