tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015-2018, Intel Corporation.
4 */
5
6#define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt
7
8#include <linux/atomic.h>
9#include <linux/errno.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/poll.h>
20#include <linux/regmap.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/timer.h>
24
25#include "kcs_bmc_device.h"
26
27
28#define DEVICE_NAME "ast-kcs-bmc"
29
30#define KCS_CHANNEL_MAX 4
31
32/*
33 * Field class descriptions
34 *
35 * LPCyE Enable LPC channel y
36 * IBFIEy Input Buffer Full IRQ Enable for LPC channel y
37 * IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX, IRQXEy)
38 * IDyIRQX Use the specified 4-bit SerIRQ for LPC channel y
39 * SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
40 * IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
41 */
42
43#define LPC_TYIRQX_LOW 0b00
44#define LPC_TYIRQX_HIGH 0b01
45#define LPC_TYIRQX_RSVD 0b10
46#define LPC_TYIRQX_RISING 0b11
47
48#define LPC_HICR0 0x000
49#define LPC_HICR0_LPC3E BIT(7)
50#define LPC_HICR0_LPC2E BIT(6)
51#define LPC_HICR0_LPC1E BIT(5)
52#define LPC_HICR2 0x008
53#define LPC_HICR2_IBFIE3 BIT(3)
54#define LPC_HICR2_IBFIE2 BIT(2)
55#define LPC_HICR2_IBFIE1 BIT(1)
56#define LPC_HICR4 0x010
57#define LPC_HICR4_LADR12AS BIT(7)
58#define LPC_HICR4_KCSENBL BIT(2)
59#define LPC_SIRQCR0 0x070
60/* IRQ{12,1}E1 are deprecated as of AST2600 A3 but necessary for prior chips */
61#define LPC_SIRQCR0_IRQ12E1 BIT(1)
62#define LPC_SIRQCR0_IRQ1E1 BIT(0)
63#define LPC_HICR5 0x080
64#define LPC_HICR5_ID3IRQX_MASK GENMASK(23, 20)
65#define LPC_HICR5_ID3IRQX_SHIFT 20
66#define LPC_HICR5_ID2IRQX_MASK GENMASK(19, 16)
67#define LPC_HICR5_ID2IRQX_SHIFT 16
68#define LPC_HICR5_SEL3IRQX BIT(15)
69#define LPC_HICR5_IRQXE3 BIT(14)
70#define LPC_HICR5_SEL2IRQX BIT(13)
71#define LPC_HICR5_IRQXE2 BIT(12)
72#define LPC_LADR3H 0x014
73#define LPC_LADR3L 0x018
74#define LPC_LADR12H 0x01C
75#define LPC_LADR12L 0x020
76#define LPC_IDR1 0x024
77#define LPC_IDR2 0x028
78#define LPC_IDR3 0x02C
79#define LPC_ODR1 0x030
80#define LPC_ODR2 0x034
81#define LPC_ODR3 0x038
82#define LPC_STR1 0x03C
83#define LPC_STR2 0x040
84#define LPC_STR3 0x044
85#define LPC_HICRB 0x100
86#define LPC_HICRB_EN16LADR2 BIT(5)
87#define LPC_HICRB_EN16LADR1 BIT(4)
88#define LPC_HICRB_IBFIE4 BIT(1)
89#define LPC_HICRB_LPC4E BIT(0)
90#define LPC_HICRC 0x104
91#define LPC_HICRC_ID4IRQX_MASK GENMASK(7, 4)
92#define LPC_HICRC_ID4IRQX_SHIFT 4
93#define LPC_HICRC_TY4IRQX_MASK GENMASK(3, 2)
94#define LPC_HICRC_TY4IRQX_SHIFT 2
95#define LPC_HICRC_OBF4_AUTO_CLR BIT(1)
96#define LPC_HICRC_IRQXE4 BIT(0)
97#define LPC_LADR4 0x110
98#define LPC_IDR4 0x114
99#define LPC_ODR4 0x118
100#define LPC_STR4 0x11C
101#define LPC_LSADR12 0x120
102#define LPC_LSADR12_LSADR2_MASK GENMASK(31, 16)
103#define LPC_LSADR12_LSADR2_SHIFT 16
104#define LPC_LSADR12_LSADR1_MASK GENMASK(15, 0)
105#define LPC_LSADR12_LSADR1_SHIFT 0
106
107#define OBE_POLL_PERIOD (HZ / 2)
108
109enum aspeed_kcs_irq_mode {
110 aspeed_kcs_irq_none,
111 aspeed_kcs_irq_serirq,
112};
113
114struct aspeed_kcs_bmc {
115 struct kcs_bmc_device kcs_bmc;
116
117 struct regmap *map;
118
119 struct {
120 enum aspeed_kcs_irq_mode mode;
121 int id;
122 } upstream_irq;
123
124 struct {
125 spinlock_t lock;
126 bool remove;
127 struct timer_list timer;
128 } obe;
129};
130
131static inline struct aspeed_kcs_bmc *to_aspeed_kcs_bmc(struct kcs_bmc_device *kcs_bmc)
132{
133 return container_of(kcs_bmc, struct aspeed_kcs_bmc, kcs_bmc);
134}
135
136static u8 aspeed_kcs_inb(struct kcs_bmc_device *kcs_bmc, u32 reg)
137{
138 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
139 u32 val = 0;
140 int rc;
141
142 rc = regmap_read(priv->map, reg, &val);
143 WARN(rc != 0, "regmap_read() failed: %d\n", rc);
144
145 return rc == 0 ? (u8) val : 0;
146}
147
148static void aspeed_kcs_outb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 data)
149{
150 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
151 int rc;
152
153 rc = regmap_write(priv->map, reg, data);
154 WARN(rc != 0, "regmap_write() failed: %d\n", rc);
155
156 /* Trigger the upstream IRQ on ODR writes, if enabled */
157
158 switch (reg) {
159 case LPC_ODR1:
160 case LPC_ODR2:
161 case LPC_ODR3:
162 case LPC_ODR4:
163 break;
164 default:
165 return;
166 }
167
168 if (priv->upstream_irq.mode != aspeed_kcs_irq_serirq)
169 return;
170
171 switch (kcs_bmc->channel) {
172 case 1:
173 switch (priv->upstream_irq.id) {
174 case 12:
175 regmap_update_bits(priv->map, LPC_SIRQCR0, LPC_SIRQCR0_IRQ12E1,
176 LPC_SIRQCR0_IRQ12E1);
177 break;
178 case 1:
179 regmap_update_bits(priv->map, LPC_SIRQCR0, LPC_SIRQCR0_IRQ1E1,
180 LPC_SIRQCR0_IRQ1E1);
181 break;
182 default:
183 break;
184 }
185 break;
186 case 2:
187 regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE2, LPC_HICR5_IRQXE2);
188 break;
189 case 3:
190 regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE3, LPC_HICR5_IRQXE3);
191 break;
192 case 4:
193 regmap_update_bits(priv->map, LPC_HICRC, LPC_HICRC_IRQXE4, LPC_HICRC_IRQXE4);
194 break;
195 default:
196 break;
197 }
198}
199
200static void aspeed_kcs_updateb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 mask, u8 val)
201{
202 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
203 int rc;
204
205 rc = regmap_update_bits(priv->map, reg, mask, val);
206 WARN(rc != 0, "regmap_update_bits() failed: %d\n", rc);
207}
208
209/*
210 * AST_usrGuide_KCS.pdf
211 * 2. Background:
212 * we note D for Data, and C for Cmd/Status, default rules are
213 * A. KCS1 / KCS2 ( D / C:X / X+4 )
214 * D / C : CA0h / CA4h
215 * D / C : CA8h / CACh
216 * B. KCS3 ( D / C:XX2h / XX3h )
217 * D / C : CA2h / CA3h
218 * D / C : CB2h / CB3h
219 * C. KCS4
220 * D / C : CA4h / CA5h
221 */
222static int aspeed_kcs_set_address(struct kcs_bmc_device *kcs_bmc, u32 addrs[2], int nr_addrs)
223{
224 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
225
226 if (WARN_ON(nr_addrs < 1 || nr_addrs > 2))
227 return -EINVAL;
228
229 switch (priv->kcs_bmc.channel) {
230 case 1:
231 regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, 0);
232 regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
233 regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
234 if (nr_addrs == 2) {
235 regmap_update_bits(priv->map, LPC_LSADR12, LPC_LSADR12_LSADR1_MASK,
236 addrs[1] << LPC_LSADR12_LSADR1_SHIFT);
237
238 regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_EN16LADR1,
239 LPC_HICRB_EN16LADR1);
240 }
241 break;
242
243 case 2:
244 regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, LPC_HICR4_LADR12AS);
245 regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
246 regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
247 if (nr_addrs == 2) {
248 regmap_update_bits(priv->map, LPC_LSADR12, LPC_LSADR12_LSADR2_MASK,
249 addrs[1] << LPC_LSADR12_LSADR2_SHIFT);
250
251 regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_EN16LADR2,
252 LPC_HICRB_EN16LADR2);
253 }
254 break;
255
256 case 3:
257 if (nr_addrs == 2) {
258 dev_err(priv->kcs_bmc.dev,
259 "Channel 3 only supports inferred status IO address\n");
260 return -EINVAL;
261 }
262
263 regmap_write(priv->map, LPC_LADR3H, addrs[0] >> 8);
264 regmap_write(priv->map, LPC_LADR3L, addrs[0] & 0xFF);
265 break;
266
267 case 4:
268 if (nr_addrs == 1)
269 regmap_write(priv->map, LPC_LADR4, ((addrs[0] + 1) << 16) | addrs[0]);
270 else
271 regmap_write(priv->map, LPC_LADR4, (addrs[1] << 16) | addrs[0]);
272
273 break;
274
275 default:
276 return -EINVAL;
277 }
278
279 return 0;
280}
281
282static inline int aspeed_kcs_map_serirq_type(u32 dt_type)
283{
284 switch (dt_type) {
285 case IRQ_TYPE_EDGE_RISING:
286 return LPC_TYIRQX_RISING;
287 case IRQ_TYPE_LEVEL_HIGH:
288 return LPC_TYIRQX_HIGH;
289 case IRQ_TYPE_LEVEL_LOW:
290 return LPC_TYIRQX_LOW;
291 default:
292 return -EINVAL;
293 }
294}
295
296static int aspeed_kcs_config_upstream_irq(struct aspeed_kcs_bmc *priv, u32 id, u32 dt_type)
297{
298 unsigned int mask, val, hw_type;
299 int ret;
300
301 if (id > 15)
302 return -EINVAL;
303
304 ret = aspeed_kcs_map_serirq_type(dt_type);
305 if (ret < 0)
306 return ret;
307 hw_type = ret;
308
309 priv->upstream_irq.mode = aspeed_kcs_irq_serirq;
310 priv->upstream_irq.id = id;
311
312 switch (priv->kcs_bmc.channel) {
313 case 1:
314 /* Needs IRQxE1 rather than (ID1IRQX, SEL1IRQX, IRQXE1) before AST2600 A3 */
315 break;
316 case 2:
317 if (!(hw_type == LPC_TYIRQX_LOW || hw_type == LPC_TYIRQX_HIGH))
318 return -EINVAL;
319
320 mask = LPC_HICR5_SEL2IRQX | LPC_HICR5_ID2IRQX_MASK;
321 val = (id << LPC_HICR5_ID2IRQX_SHIFT);
322 val |= (hw_type == LPC_TYIRQX_HIGH) ? LPC_HICR5_SEL2IRQX : 0;
323 regmap_update_bits(priv->map, LPC_HICR5, mask, val);
324
325 break;
326 case 3:
327 if (!(hw_type == LPC_TYIRQX_LOW || hw_type == LPC_TYIRQX_HIGH))
328 return -EINVAL;
329
330 mask = LPC_HICR5_SEL3IRQX | LPC_HICR5_ID3IRQX_MASK;
331 val = (id << LPC_HICR5_ID3IRQX_SHIFT);
332 val |= (hw_type == LPC_TYIRQX_HIGH) ? LPC_HICR5_SEL3IRQX : 0;
333 regmap_update_bits(priv->map, LPC_HICR5, mask, val);
334
335 break;
336 case 4:
337 mask = LPC_HICRC_ID4IRQX_MASK | LPC_HICRC_TY4IRQX_MASK | LPC_HICRC_OBF4_AUTO_CLR;
338 val = (id << LPC_HICRC_ID4IRQX_SHIFT) | (hw_type << LPC_HICRC_TY4IRQX_SHIFT);
339 regmap_update_bits(priv->map, LPC_HICRC, mask, val);
340 break;
341 default:
342 dev_warn(priv->kcs_bmc.dev,
343 "SerIRQ configuration not supported on KCS channel %d\n",
344 priv->kcs_bmc.channel);
345 return -EINVAL;
346 }
347
348 return 0;
349}
350
351static void aspeed_kcs_enable_channel(struct kcs_bmc_device *kcs_bmc, bool enable)
352{
353 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
354
355 switch (kcs_bmc->channel) {
356 case 1:
357 regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC1E, enable * LPC_HICR0_LPC1E);
358 return;
359 case 2:
360 regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC2E, enable * LPC_HICR0_LPC2E);
361 return;
362 case 3:
363 regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC3E, enable * LPC_HICR0_LPC3E);
364 regmap_update_bits(priv->map, LPC_HICR4,
365 LPC_HICR4_KCSENBL, enable * LPC_HICR4_KCSENBL);
366 return;
367 case 4:
368 regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_LPC4E, enable * LPC_HICRB_LPC4E);
369 return;
370 default:
371 pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
372 return;
373 }
374}
375
376static void aspeed_kcs_check_obe(struct timer_list *timer)
377{
378 struct aspeed_kcs_bmc *priv = container_of(timer, struct aspeed_kcs_bmc, obe.timer);
379 unsigned long flags;
380 u8 str;
381
382 spin_lock_irqsave(&priv->obe.lock, flags);
383 if (priv->obe.remove) {
384 spin_unlock_irqrestore(&priv->obe.lock, flags);
385 return;
386 }
387
388 str = aspeed_kcs_inb(&priv->kcs_bmc, priv->kcs_bmc.ioreg.str);
389 if (str & KCS_BMC_STR_OBF) {
390 mod_timer(timer, jiffies + OBE_POLL_PERIOD);
391 spin_unlock_irqrestore(&priv->obe.lock, flags);
392 return;
393 }
394 spin_unlock_irqrestore(&priv->obe.lock, flags);
395
396 kcs_bmc_handle_event(&priv->kcs_bmc);
397}
398
399static void aspeed_kcs_irq_mask_update(struct kcs_bmc_device *kcs_bmc, u8 mask, u8 state)
400{
401 struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
402
403 /* We don't have an OBE IRQ, emulate it */
404 if (mask & KCS_BMC_EVENT_TYPE_OBE) {
405 if (KCS_BMC_EVENT_TYPE_OBE & state)
406 mod_timer(&priv->obe.timer, jiffies + OBE_POLL_PERIOD);
407 else
408 del_timer(&priv->obe.timer);
409 }
410
411 if (mask & KCS_BMC_EVENT_TYPE_IBF) {
412 const bool enable = !!(state & KCS_BMC_EVENT_TYPE_IBF);
413
414 switch (kcs_bmc->channel) {
415 case 1:
416 regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE1,
417 enable * LPC_HICR2_IBFIE1);
418 return;
419 case 2:
420 regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE2,
421 enable * LPC_HICR2_IBFIE2);
422 return;
423 case 3:
424 regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE3,
425 enable * LPC_HICR2_IBFIE3);
426 return;
427 case 4:
428 regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_IBFIE4,
429 enable * LPC_HICRB_IBFIE4);
430 return;
431 default:
432 pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
433 return;
434 }
435 }
436}
437
438static const struct kcs_bmc_device_ops aspeed_kcs_ops = {
439 .irq_mask_update = aspeed_kcs_irq_mask_update,
440 .io_inputb = aspeed_kcs_inb,
441 .io_outputb = aspeed_kcs_outb,
442 .io_updateb = aspeed_kcs_updateb,
443};
444
445static irqreturn_t aspeed_kcs_irq(int irq, void *arg)
446{
447 struct kcs_bmc_device *kcs_bmc = arg;
448
449 return kcs_bmc_handle_event(kcs_bmc);
450}
451
452static int aspeed_kcs_config_downstream_irq(struct kcs_bmc_device *kcs_bmc,
453 struct platform_device *pdev)
454{
455 struct device *dev = &pdev->dev;
456 int irq;
457
458 irq = platform_get_irq(pdev, 0);
459 if (irq < 0)
460 return irq;
461
462 return devm_request_irq(dev, irq, aspeed_kcs_irq, IRQF_SHARED,
463 dev_name(dev), kcs_bmc);
464}
465
466static const struct kcs_ioreg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = {
467 { .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 },
468 { .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 },
469 { .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 },
470 { .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 },
471};
472
473static int aspeed_kcs_of_get_channel(struct platform_device *pdev)
474{
475 struct device_node *np;
476 struct kcs_ioreg ioreg;
477 const __be32 *reg;
478 int i;
479
480 np = pdev->dev.of_node;
481
482 /* Don't translate addresses, we want offsets for the regmaps */
483 reg = of_get_address(np, 0, NULL, NULL);
484 if (!reg)
485 return -EINVAL;
486 ioreg.idr = be32_to_cpup(reg);
487
488 reg = of_get_address(np, 1, NULL, NULL);
489 if (!reg)
490 return -EINVAL;
491 ioreg.odr = be32_to_cpup(reg);
492
493 reg = of_get_address(np, 2, NULL, NULL);
494 if (!reg)
495 return -EINVAL;
496 ioreg.str = be32_to_cpup(reg);
497
498 for (i = 0; i < ARRAY_SIZE(ast_kcs_bmc_ioregs); i++) {
499 if (!memcmp(&ast_kcs_bmc_ioregs[i], &ioreg, sizeof(ioreg)))
500 return i + 1;
501 }
502 return -EINVAL;
503}
504
505static int
506aspeed_kcs_of_get_io_address(struct platform_device *pdev, u32 addrs[2])
507{
508 int rc;
509
510 rc = of_property_read_variable_u32_array(pdev->dev.of_node,
511 "aspeed,lpc-io-reg",
512 addrs, 1, 2);
513 if (rc < 0) {
514 dev_err(&pdev->dev, "No valid 'aspeed,lpc-io-reg' configured\n");
515 return rc;
516 }
517
518 if (addrs[0] > 0xffff) {
519 dev_err(&pdev->dev, "Invalid data address in 'aspeed,lpc-io-reg'\n");
520 return -EINVAL;
521 }
522
523 if (rc == 2 && addrs[1] > 0xffff) {
524 dev_err(&pdev->dev, "Invalid status address in 'aspeed,lpc-io-reg'\n");
525 return -EINVAL;
526 }
527
528 return rc;
529}
530
531static int aspeed_kcs_probe(struct platform_device *pdev)
532{
533 struct kcs_bmc_device *kcs_bmc;
534 struct aspeed_kcs_bmc *priv;
535 struct device_node *np;
536 bool have_upstream_irq;
537 u32 upstream_irq[2];
538 int rc, channel;
539 int nr_addrs;
540 u32 addrs[2];
541
542 np = pdev->dev.of_node->parent;
543 if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
544 !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
545 !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
546 dev_err(&pdev->dev, "unsupported LPC device binding\n");
547 return -ENODEV;
548 }
549
550 channel = aspeed_kcs_of_get_channel(pdev);
551 if (channel < 0)
552 return channel;
553
554 nr_addrs = aspeed_kcs_of_get_io_address(pdev, addrs);
555 if (nr_addrs < 0)
556 return nr_addrs;
557
558 np = pdev->dev.of_node;
559 rc = of_property_read_u32_array(np, "aspeed,lpc-interrupts", upstream_irq, 2);
560 if (rc && rc != -EINVAL)
561 return -EINVAL;
562
563 have_upstream_irq = !rc;
564
565 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
566 if (!priv)
567 return -ENOMEM;
568
569 kcs_bmc = &priv->kcs_bmc;
570 kcs_bmc->dev = &pdev->dev;
571 kcs_bmc->channel = channel;
572 kcs_bmc->ioreg = ast_kcs_bmc_ioregs[channel - 1];
573 kcs_bmc->ops = &aspeed_kcs_ops;
574
575 priv->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
576 if (IS_ERR(priv->map)) {
577 dev_err(&pdev->dev, "Couldn't get regmap\n");
578 return -ENODEV;
579 }
580
581 spin_lock_init(&priv->obe.lock);
582 priv->obe.remove = false;
583 timer_setup(&priv->obe.timer, aspeed_kcs_check_obe, 0);
584
585 rc = aspeed_kcs_set_address(kcs_bmc, addrs, nr_addrs);
586 if (rc)
587 return rc;
588
589 /* Host to BMC IRQ */
590 rc = aspeed_kcs_config_downstream_irq(kcs_bmc, pdev);
591 if (rc)
592 return rc;
593
594 /* BMC to Host IRQ */
595 if (have_upstream_irq) {
596 rc = aspeed_kcs_config_upstream_irq(priv, upstream_irq[0], upstream_irq[1]);
597 if (rc < 0)
598 return rc;
599 } else {
600 priv->upstream_irq.mode = aspeed_kcs_irq_none;
601 }
602
603 platform_set_drvdata(pdev, priv);
604
605 aspeed_kcs_irq_mask_update(kcs_bmc, (KCS_BMC_EVENT_TYPE_IBF | KCS_BMC_EVENT_TYPE_OBE), 0);
606 aspeed_kcs_enable_channel(kcs_bmc, true);
607
608 rc = kcs_bmc_add_device(&priv->kcs_bmc);
609 if (rc) {
610 dev_warn(&pdev->dev, "Failed to register channel %d: %d\n", kcs_bmc->channel, rc);
611 return rc;
612 }
613
614 dev_info(&pdev->dev, "Initialised channel %d at 0x%x\n",
615 kcs_bmc->channel, addrs[0]);
616
617 return 0;
618}
619
620static int aspeed_kcs_remove(struct platform_device *pdev)
621{
622 struct aspeed_kcs_bmc *priv = platform_get_drvdata(pdev);
623 struct kcs_bmc_device *kcs_bmc = &priv->kcs_bmc;
624
625 kcs_bmc_remove_device(kcs_bmc);
626
627 aspeed_kcs_enable_channel(kcs_bmc, false);
628 aspeed_kcs_irq_mask_update(kcs_bmc, (KCS_BMC_EVENT_TYPE_IBF | KCS_BMC_EVENT_TYPE_OBE), 0);
629
630 /* Make sure it's proper dead */
631 spin_lock_irq(&priv->obe.lock);
632 priv->obe.remove = true;
633 spin_unlock_irq(&priv->obe.lock);
634 del_timer_sync(&priv->obe.timer);
635
636 return 0;
637}
638
639static const struct of_device_id ast_kcs_bmc_match[] = {
640 { .compatible = "aspeed,ast2400-kcs-bmc-v2" },
641 { .compatible = "aspeed,ast2500-kcs-bmc-v2" },
642 { .compatible = "aspeed,ast2600-kcs-bmc" },
643 { }
644};
645MODULE_DEVICE_TABLE(of, ast_kcs_bmc_match);
646
647static struct platform_driver ast_kcs_bmc_driver = {
648 .driver = {
649 .name = DEVICE_NAME,
650 .of_match_table = ast_kcs_bmc_match,
651 },
652 .probe = aspeed_kcs_probe,
653 .remove = aspeed_kcs_remove,
654};
655module_platform_driver(ast_kcs_bmc_driver);
656
657MODULE_LICENSE("GPL v2");
658MODULE_AUTHOR("Haiyue Wang <haiyue.wang@linux.intel.com>");
659MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
660MODULE_DESCRIPTION("Aspeed device interface to the KCS BMC device");