tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef _VC4_HDMI_REGS_H_
2#define _VC4_HDMI_REGS_H_
3
4#include <linux/pm_runtime.h>
5
6#include "vc4_hdmi.h"
7
8#define VC4_HDMI_PACKET_STRIDE 0x24
9
10enum vc4_hdmi_regs {
11 VC4_INVALID = 0,
12 VC4_HDMI,
13 VC4_HD,
14 VC5_CEC,
15 VC5_CSC,
16 VC5_DVP,
17 VC5_PHY,
18 VC5_RAM,
19 VC5_RM,
20};
21
22enum vc4_hdmi_field {
23 HDMI_AUDIO_PACKET_CONFIG,
24 HDMI_CEC_CNTRL_1,
25 HDMI_CEC_CNTRL_2,
26 HDMI_CEC_CNTRL_3,
27 HDMI_CEC_CNTRL_4,
28 HDMI_CEC_CNTRL_5,
29 HDMI_CEC_CPU_CLEAR,
30 HDMI_CEC_CPU_MASK_CLEAR,
31 HDMI_CEC_CPU_MASK_SET,
32 HDMI_CEC_CPU_MASK_STATUS,
33 HDMI_CEC_CPU_STATUS,
34 HDMI_CEC_CPU_SET,
35
36 /*
37 * Transmit data, first byte is low byte of the 32-bit reg.
38 * MSB of each byte transmitted first.
39 */
40 HDMI_CEC_RX_DATA_1,
41 HDMI_CEC_RX_DATA_2,
42 HDMI_CEC_RX_DATA_3,
43 HDMI_CEC_RX_DATA_4,
44 HDMI_CEC_TX_DATA_1,
45 HDMI_CEC_TX_DATA_2,
46 HDMI_CEC_TX_DATA_3,
47 HDMI_CEC_TX_DATA_4,
48 HDMI_CLOCK_STOP,
49 HDMI_CORE_REV,
50 HDMI_CRP_CFG,
51 HDMI_CSC_12_11,
52 HDMI_CSC_14_13,
53 HDMI_CSC_22_21,
54 HDMI_CSC_24_23,
55 HDMI_CSC_32_31,
56 HDMI_CSC_34_33,
57 HDMI_CSC_CHANNEL_CTL,
58 HDMI_CSC_CTL,
59
60 /*
61 * 20-bit fields containing CTS values to be transmitted if
62 * !EXTERNAL_CTS_EN
63 */
64 HDMI_CTS_0,
65 HDMI_CTS_1,
66 HDMI_DEEP_COLOR_CONFIG_1,
67 HDMI_DVP_CTL,
68 HDMI_FIFO_CTL,
69 HDMI_FRAME_COUNT,
70 HDMI_GCP_CONFIG,
71 HDMI_GCP_WORD_1,
72 HDMI_HORZA,
73 HDMI_HORZB,
74 HDMI_HOTPLUG,
75 HDMI_HOTPLUG_INT,
76
77 /*
78 * 3 bits per field, where each field maps from that
79 * corresponding MAI bus channel to the given HDMI channel.
80 */
81 HDMI_MAI_CHANNEL_MAP,
82 HDMI_MAI_CONFIG,
83 HDMI_MAI_CTL,
84
85 /*
86 * Register for DMAing in audio data to be transported over
87 * the MAI bus to the Falcon core.
88 */
89 HDMI_MAI_DATA,
90
91 /* Format header to be placed on the MAI data. Unused. */
92 HDMI_MAI_FMT,
93
94 /* Last received format word on the MAI bus. */
95 HDMI_MAI_FORMAT,
96 HDMI_MAI_SMP,
97 HDMI_MAI_THR,
98 HDMI_M_CTL,
99 HDMI_RAM_PACKET_CONFIG,
100 HDMI_RAM_PACKET_START,
101 HDMI_RAM_PACKET_STATUS,
102 HDMI_RM_CONTROL,
103 HDMI_RM_FORMAT,
104 HDMI_RM_OFFSET,
105 HDMI_SCHEDULER_CONTROL,
106 HDMI_SCRAMBLER_CTL,
107 HDMI_SW_RESET_CONTROL,
108 HDMI_TX_PHY_CHANNEL_SWAP,
109 HDMI_TX_PHY_CLK_DIV,
110 HDMI_TX_PHY_CTL_0,
111 HDMI_TX_PHY_CTL_1,
112 HDMI_TX_PHY_CTL_2,
113 HDMI_TX_PHY_CTL_3,
114 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
115 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
116 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
117 HDMI_TX_PHY_PLL_CFG,
118 HDMI_TX_PHY_PLL_CTL_0,
119 HDMI_TX_PHY_PLL_CTL_1,
120 HDMI_TX_PHY_POWERDOWN_CTL,
121 HDMI_TX_PHY_RESET_CTL,
122 HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
123 HDMI_VEC_INTERFACE_CFG,
124 HDMI_VEC_INTERFACE_XBAR,
125 HDMI_VERTA0,
126 HDMI_VERTA1,
127 HDMI_VERTB0,
128 HDMI_VERTB1,
129 HDMI_VID_CTL,
130};
131
132struct vc4_hdmi_register {
133 char *name;
134 enum vc4_hdmi_regs reg;
135 unsigned int offset;
136};
137
138#define _VC4_REG(_base, _reg, _offset) \
139 [_reg] = { \
140 .name = #_reg, \
141 .reg = _base, \
142 .offset = _offset, \
143 }
144
145#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
146#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
147#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
148#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
149#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
150#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
151#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
152#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
153
154static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
155 VC4_HD_REG(HDMI_M_CTL, 0x000c),
156 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
157 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
158 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
159 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
160 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
161 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
162 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
163 VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
164 VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
165 VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
166 VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
167 VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
168 VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
169 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
170
171 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
172 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
173 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
174 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
175 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
176 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
177 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
178 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
179 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
180 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
181 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
182 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
183 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
184 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
185 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
186 VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
187 VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
188 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
189 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
190 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
191 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
192 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
193 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
194 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
195 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
196 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
197 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
198 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
199 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
200 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
201 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
202 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
203 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
204 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
205 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
206 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
207 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
208 VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
209 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
210 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
211 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
212 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
213 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
214};
215
216static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
217 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
218 VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
219 VC4_HD_REG(HDMI_MAI_THR, 0x0014),
220 VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
221 VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
222 VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
223 VC4_HD_REG(HDMI_VID_CTL, 0x0044),
224 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
225
226 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
227 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
228 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
229 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
230 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
231 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
232 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
233 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
234 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
235 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
236 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
237 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
238 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
239 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
240 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
241 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
242 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
243 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
244 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
245 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
246 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
247
248 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
249 VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
250 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
251
252 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
253 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
254 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
255 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
256 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
257 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
258 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
259 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
260 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
261 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
262 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
263 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
264 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
265 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
266 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
267
268 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
269 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
270 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
271
272 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
273
274 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
275 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
276 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
277 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
278 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
279 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
280 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
281 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
282 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
283 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
284 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
285 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
286 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
287
288 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
289 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
290 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
291 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
292 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
293 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
294 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
295 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
296};
297
298static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
299 VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
300 VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
301 VC4_HD_REG(HDMI_MAI_THR, 0x0034),
302 VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
303 VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
304 VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
305 VC4_HD_REG(HDMI_VID_CTL, 0x0048),
306 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
307
308 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
309 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
310 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
311 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
312 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
313 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
314 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
315 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
316 VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
317 VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
318 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
319 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
320 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
321 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
322 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
323 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
324 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
325 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
326 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
327 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
328 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
329
330 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
331 VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
332 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
333
334 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
335 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
336 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
337 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
338 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
339 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
340 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
341 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
342 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
343 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
344 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
345 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
346 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
347 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
348 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
349
350 VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
351 VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
352 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
353
354 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
355
356 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
357 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
358 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
359 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
360 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
361 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
362 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
363 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
364 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
365 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
366 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
367 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
368 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
369
370 VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
371 VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
372 VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
373 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
374 VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
375 VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
376 VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
377 VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
378};
379
380static inline
381void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
382 enum vc4_hdmi_regs reg)
383{
384 switch (reg) {
385 case VC4_HD:
386 return hdmi->hd_regs;
387
388 case VC4_HDMI:
389 return hdmi->hdmicore_regs;
390
391 case VC5_CSC:
392 return hdmi->csc_regs;
393
394 case VC5_CEC:
395 return hdmi->cec_regs;
396
397 case VC5_DVP:
398 return hdmi->dvp_regs;
399
400 case VC5_PHY:
401 return hdmi->phy_regs;
402
403 case VC5_RAM:
404 return hdmi->ram_regs;
405
406 case VC5_RM:
407 return hdmi->rm_regs;
408
409 default:
410 return NULL;
411 }
412
413 return NULL;
414}
415
416static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
417 enum vc4_hdmi_field reg)
418{
419 const struct vc4_hdmi_register *field;
420 const struct vc4_hdmi_variant *variant = hdmi->variant;
421 void __iomem *base;
422
423 WARN_ON(!pm_runtime_active(&hdmi->pdev->dev));
424
425 if (reg >= variant->num_registers) {
426 dev_warn(&hdmi->pdev->dev,
427 "Invalid register ID %u\n", reg);
428 return 0;
429 }
430
431 field = &variant->registers[reg];
432 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
433 if (!base) {
434 dev_warn(&hdmi->pdev->dev,
435 "Unknown register ID %u\n", reg);
436 return 0;
437 }
438
439 return readl(base + field->offset);
440}
441#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg)
442
443static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
444 enum vc4_hdmi_field reg,
445 u32 value)
446{
447 const struct vc4_hdmi_register *field;
448 const struct vc4_hdmi_variant *variant = hdmi->variant;
449 void __iomem *base;
450
451 lockdep_assert_held(&hdmi->hw_lock);
452
453 WARN_ON(!pm_runtime_active(&hdmi->pdev->dev));
454
455 if (reg >= variant->num_registers) {
456 dev_warn(&hdmi->pdev->dev,
457 "Invalid register ID %u\n", reg);
458 return;
459 }
460
461 field = &variant->registers[reg];
462 base = __vc4_hdmi_get_field_base(hdmi, field->reg);
463 if (!base)
464 return;
465
466 writel(value, base + field->offset);
467}
468#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val)
469
470#endif /* _VC4_HDMI_REGS_H_ */