Linux kernel mirror (for testing)
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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
29extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
30extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
31
32enum smu_event_type {
33 SMU_EVENT_RESET_COMPLETE = 0,
34};
35
36struct amd_vce_state {
37 /* vce clocks */
38 u32 evclk;
39 u32 ecclk;
40 /* gpu clocks */
41 u32 sclk;
42 u32 mclk;
43 u8 clk_idx;
44 u8 pstate;
45};
46
47
48enum amd_dpm_forced_level {
49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
51 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
59};
60
61enum amd_pm_state_type {
62 /* not used for dpm */
63 POWER_STATE_TYPE_DEFAULT,
64 POWER_STATE_TYPE_POWERSAVE,
65 /* user selectable states */
66 POWER_STATE_TYPE_BATTERY,
67 POWER_STATE_TYPE_BALANCED,
68 POWER_STATE_TYPE_PERFORMANCE,
69 /* internal states */
70 POWER_STATE_TYPE_INTERNAL_UVD,
71 POWER_STATE_TYPE_INTERNAL_UVD_SD,
72 POWER_STATE_TYPE_INTERNAL_UVD_HD,
73 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
74 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
75 POWER_STATE_TYPE_INTERNAL_BOOT,
76 POWER_STATE_TYPE_INTERNAL_THERMAL,
77 POWER_STATE_TYPE_INTERNAL_ACPI,
78 POWER_STATE_TYPE_INTERNAL_ULV,
79 POWER_STATE_TYPE_INTERNAL_3DPERF,
80};
81
82#define AMD_MAX_VCE_LEVELS 6
83
84enum amd_vce_level {
85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
91};
92
93enum amd_fan_ctrl_mode {
94 AMD_FAN_CTRL_NONE = 0,
95 AMD_FAN_CTRL_MANUAL = 1,
96 AMD_FAN_CTRL_AUTO = 2,
97};
98
99enum pp_clock_type {
100 PP_SCLK,
101 PP_MCLK,
102 PP_PCIE,
103 PP_SOCCLK,
104 PP_FCLK,
105 PP_DCEFCLK,
106 PP_VCLK,
107 PP_DCLK,
108 OD_SCLK,
109 OD_MCLK,
110 OD_VDDC_CURVE,
111 OD_RANGE,
112 OD_VDDGFX_OFFSET,
113 OD_CCLK,
114};
115
116enum amd_pp_sensors {
117 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
118 AMDGPU_PP_SENSOR_CPU_CLK,
119 AMDGPU_PP_SENSOR_VDDNB,
120 AMDGPU_PP_SENSOR_VDDGFX,
121 AMDGPU_PP_SENSOR_UVD_VCLK,
122 AMDGPU_PP_SENSOR_UVD_DCLK,
123 AMDGPU_PP_SENSOR_VCE_ECCLK,
124 AMDGPU_PP_SENSOR_GPU_LOAD,
125 AMDGPU_PP_SENSOR_MEM_LOAD,
126 AMDGPU_PP_SENSOR_GFX_MCLK,
127 AMDGPU_PP_SENSOR_GPU_TEMP,
128 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
129 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
130 AMDGPU_PP_SENSOR_MEM_TEMP,
131 AMDGPU_PP_SENSOR_VCE_POWER,
132 AMDGPU_PP_SENSOR_UVD_POWER,
133 AMDGPU_PP_SENSOR_GPU_POWER,
134 AMDGPU_PP_SENSOR_SS_APU_SHARE,
135 AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
136 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
137 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
138 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
139 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
140 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
141 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
142};
143
144enum amd_pp_task {
145 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
146 AMD_PP_TASK_ENABLE_USER_STATE,
147 AMD_PP_TASK_READJUST_POWER_STATE,
148 AMD_PP_TASK_COMPLETE_INIT,
149 AMD_PP_TASK_MAX
150};
151
152enum PP_SMC_POWER_PROFILE {
153 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
154 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
155 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
156 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
157 PP_SMC_POWER_PROFILE_VR = 0x4,
158 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
159 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
160 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7,
161 PP_SMC_POWER_PROFILE_COUNT,
162};
163
164extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
165
166
167
168enum {
169 PP_GROUP_UNKNOWN = 0,
170 PP_GROUP_GFX = 1,
171 PP_GROUP_SYS,
172 PP_GROUP_MAX
173};
174
175enum PP_OD_DPM_TABLE_COMMAND {
176 PP_OD_EDIT_SCLK_VDDC_TABLE,
177 PP_OD_EDIT_MCLK_VDDC_TABLE,
178 PP_OD_EDIT_CCLK_VDDC_TABLE,
179 PP_OD_EDIT_VDDC_CURVE,
180 PP_OD_RESTORE_DEFAULT_TABLE,
181 PP_OD_COMMIT_DPM_TABLE,
182 PP_OD_EDIT_VDDGFX_OFFSET
183};
184
185struct pp_states_info {
186 uint32_t nums;
187 uint32_t states[16];
188};
189
190enum PP_HWMON_TEMP {
191 PP_TEMP_EDGE = 0,
192 PP_TEMP_JUNCTION,
193 PP_TEMP_MEM,
194 PP_TEMP_MAX
195};
196
197enum pp_mp1_state {
198 PP_MP1_STATE_NONE,
199 PP_MP1_STATE_SHUTDOWN,
200 PP_MP1_STATE_UNLOAD,
201 PP_MP1_STATE_RESET,
202};
203
204enum pp_df_cstate {
205 DF_CSTATE_DISALLOW = 0,
206 DF_CSTATE_ALLOW,
207};
208
209/**
210 * DOC: amdgpu_pp_power
211 *
212 * APU power is managed to system-level requirements through the PPT
213 * (package power tracking) feature. PPT is intended to limit power to the
214 * requirements of the power source and could be dynamically updated to
215 * maximize APU performance within the system power budget.
216 *
217 * Two types of power measurement can be requested, where supported, with
218 * :c:type:`enum pp_power_type <pp_power_type>`.
219 */
220
221/**
222 * enum pp_power_limit_level - Used to query the power limits
223 *
224 * @PP_PWR_LIMIT_MIN: Minimum Power Limit
225 * @PP_PWR_LIMIT_CURRENT: Current Power Limit
226 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
227 * @PP_PWR_LIMIT_MAX: Maximum Power Limit
228 */
229enum pp_power_limit_level
230{
231 PP_PWR_LIMIT_MIN = -1,
232 PP_PWR_LIMIT_CURRENT,
233 PP_PWR_LIMIT_DEFAULT,
234 PP_PWR_LIMIT_MAX,
235};
236
237/**
238 * enum pp_power_type - Used to specify the type of the requested power
239 *
240 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
241 * moving average of APU power (default ~5000 ms).
242 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
243 * where supported.
244 */
245enum pp_power_type
246{
247 PP_PWR_TYPE_SUSTAINED,
248 PP_PWR_TYPE_FAST,
249};
250
251#define PP_GROUP_MASK 0xF0000000
252#define PP_GROUP_SHIFT 28
253
254#define PP_BLOCK_MASK 0x0FFFFF00
255#define PP_BLOCK_SHIFT 8
256
257#define PP_BLOCK_GFX_CG 0x01
258#define PP_BLOCK_GFX_MG 0x02
259#define PP_BLOCK_GFX_3D 0x04
260#define PP_BLOCK_GFX_RLC 0x08
261#define PP_BLOCK_GFX_CP 0x10
262#define PP_BLOCK_SYS_BIF 0x01
263#define PP_BLOCK_SYS_MC 0x02
264#define PP_BLOCK_SYS_ROM 0x04
265#define PP_BLOCK_SYS_DRM 0x08
266#define PP_BLOCK_SYS_HDP 0x10
267#define PP_BLOCK_SYS_SDMA 0x20
268
269#define PP_STATE_MASK 0x0000000F
270#define PP_STATE_SHIFT 0
271#define PP_STATE_SUPPORT_MASK 0x000000F0
272#define PP_STATE_SUPPORT_SHIFT 0
273
274#define PP_STATE_CG 0x01
275#define PP_STATE_LS 0x02
276#define PP_STATE_DS 0x04
277#define PP_STATE_SD 0x08
278#define PP_STATE_SUPPORT_CG 0x10
279#define PP_STATE_SUPPORT_LS 0x20
280#define PP_STATE_SUPPORT_DS 0x40
281#define PP_STATE_SUPPORT_SD 0x80
282
283#define PP_CG_MSG_ID(group, block, support, state) \
284 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
285 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
286
287#define XGMI_MODE_PSTATE_D3 0
288#define XGMI_MODE_PSTATE_D0 1
289
290#define NUM_HBM_INSTANCES 4
291
292struct seq_file;
293enum amd_pp_clock_type;
294struct amd_pp_simple_clock_info;
295struct amd_pp_display_configuration;
296struct amd_pp_clock_info;
297struct pp_display_clock_request;
298struct pp_clock_levels_with_voltage;
299struct pp_clock_levels_with_latency;
300struct amd_pp_clocks;
301struct pp_smu_wm_range_sets;
302struct pp_smu_nv_clock_table;
303struct dpm_clocks;
304
305struct amd_pm_funcs {
306/* export for dpm on ci and si */
307 int (*pre_set_power_state)(void *handle);
308 int (*set_power_state)(void *handle);
309 void (*post_set_power_state)(void *handle);
310 void (*display_configuration_changed)(void *handle);
311 void (*print_power_state)(void *handle, void *ps);
312 bool (*vblank_too_short)(void *handle);
313 void (*enable_bapm)(void *handle, bool enable);
314 int (*check_state_equal)(void *handle,
315 void *cps,
316 void *rps,
317 bool *equal);
318/* export for sysfs */
319 int (*set_fan_control_mode)(void *handle, u32 mode);
320 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
321 int (*set_fan_speed_pwm)(void *handle, u32 speed);
322 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
323 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
324 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
325 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
326 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
327 int (*get_sclk_od)(void *handle);
328 int (*set_sclk_od)(void *handle, uint32_t value);
329 int (*get_mclk_od)(void *handle);
330 int (*set_mclk_od)(void *handle, uint32_t value);
331 int (*read_sensor)(void *handle, int idx, void *value, int *size);
332 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
333 enum amd_pm_state_type (*get_current_power_state)(void *handle);
334 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
335 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
336 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
337 int (*get_pp_table)(void *handle, char **table);
338 int (*set_pp_table)(void *handle, const char *buf, size_t size);
339 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
340 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
341/* export to amdgpu */
342 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
343 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
344 enum amd_pm_state_type *user_state);
345 int (*load_firmware)(void *handle);
346 int (*wait_for_fw_loading_complete)(void *handle);
347 int (*set_powergating_by_smu)(void *handle,
348 uint32_t block_type, bool gate);
349 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
350 int (*set_power_limit)(void *handle, uint32_t n);
351 int (*get_power_limit)(void *handle, uint32_t *limit,
352 enum pp_power_limit_level pp_limit_level,
353 enum pp_power_type power_type);
354 int (*get_power_profile_mode)(void *handle, char *buf);
355 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
356 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
357 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
358 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
359 int (*smu_i2c_bus_access)(void *handle, bool acquire);
360 int (*gfx_state_change_set)(void *handle, uint32_t state);
361/* export to DC */
362 u32 (*get_sclk)(void *handle, bool low);
363 u32 (*get_mclk)(void *handle, bool low);
364 int (*display_configuration_change)(void *handle,
365 const struct amd_pp_display_configuration *input);
366 int (*get_display_power_level)(void *handle,
367 struct amd_pp_simple_clock_info *output);
368 int (*get_current_clocks)(void *handle,
369 struct amd_pp_clock_info *clocks);
370 int (*get_clock_by_type)(void *handle,
371 enum amd_pp_clock_type type,
372 struct amd_pp_clocks *clocks);
373 int (*get_clock_by_type_with_latency)(void *handle,
374 enum amd_pp_clock_type type,
375 struct pp_clock_levels_with_latency *clocks);
376 int (*get_clock_by_type_with_voltage)(void *handle,
377 enum amd_pp_clock_type type,
378 struct pp_clock_levels_with_voltage *clocks);
379 int (*set_watermarks_for_clocks_ranges)(void *handle,
380 void *clock_ranges);
381 int (*display_clock_voltage_request)(void *handle,
382 struct pp_display_clock_request *clock);
383 int (*get_display_mode_validation_clocks)(void *handle,
384 struct amd_pp_simple_clock_info *clocks);
385 int (*notify_smu_enable_pwe)(void *handle);
386 int (*enable_mgpu_fan_boost)(void *handle);
387 int (*set_active_display_count)(void *handle, uint32_t count);
388 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
389 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
390 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
391 int (*get_asic_baco_capability)(void *handle, bool *cap);
392 int (*get_asic_baco_state)(void *handle, int *state);
393 int (*set_asic_baco_state)(void *handle, int state);
394 int (*get_ppfeature_status)(void *handle, char *buf);
395 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
396 int (*asic_reset_mode_2)(void *handle);
397 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
398 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
399 ssize_t (*get_gpu_metrics)(void *handle, void **table);
400 int (*set_watermarks_for_clock_ranges)(void *handle,
401 struct pp_smu_wm_range_sets *ranges);
402 int (*display_disable_memory_clock_switch)(void *handle,
403 bool disable_memory_clock_switch);
404 int (*get_max_sustainable_clocks_by_dc)(void *handle,
405 struct pp_smu_nv_clock_table *max_clocks);
406 int (*get_uclk_dpm_states)(void *handle,
407 unsigned int *clock_values_in_khz,
408 unsigned int *num_states);
409 int (*get_dpm_clock_table)(void *handle,
410 struct dpm_clocks *clock_table);
411 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
412 void (*pm_compute_clocks)(void *handle);
413};
414
415struct metrics_table_header {
416 uint16_t structure_size;
417 uint8_t format_revision;
418 uint8_t content_revision;
419};
420
421/*
422 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
423 * Use gpu_metrics_v1_1 or later instead.
424 */
425struct gpu_metrics_v1_0 {
426 struct metrics_table_header common_header;
427
428 /* Driver attached timestamp (in ns) */
429 uint64_t system_clock_counter;
430
431 /* Temperature */
432 uint16_t temperature_edge;
433 uint16_t temperature_hotspot;
434 uint16_t temperature_mem;
435 uint16_t temperature_vrgfx;
436 uint16_t temperature_vrsoc;
437 uint16_t temperature_vrmem;
438
439 /* Utilization */
440 uint16_t average_gfx_activity;
441 uint16_t average_umc_activity; // memory controller
442 uint16_t average_mm_activity; // UVD or VCN
443
444 /* Power/Energy */
445 uint16_t average_socket_power;
446 uint32_t energy_accumulator;
447
448 /* Average clocks */
449 uint16_t average_gfxclk_frequency;
450 uint16_t average_socclk_frequency;
451 uint16_t average_uclk_frequency;
452 uint16_t average_vclk0_frequency;
453 uint16_t average_dclk0_frequency;
454 uint16_t average_vclk1_frequency;
455 uint16_t average_dclk1_frequency;
456
457 /* Current clocks */
458 uint16_t current_gfxclk;
459 uint16_t current_socclk;
460 uint16_t current_uclk;
461 uint16_t current_vclk0;
462 uint16_t current_dclk0;
463 uint16_t current_vclk1;
464 uint16_t current_dclk1;
465
466 /* Throttle status */
467 uint32_t throttle_status;
468
469 /* Fans */
470 uint16_t current_fan_speed;
471
472 /* Link width/speed */
473 uint8_t pcie_link_width;
474 uint8_t pcie_link_speed; // in 0.1 GT/s
475};
476
477struct gpu_metrics_v1_1 {
478 struct metrics_table_header common_header;
479
480 /* Temperature */
481 uint16_t temperature_edge;
482 uint16_t temperature_hotspot;
483 uint16_t temperature_mem;
484 uint16_t temperature_vrgfx;
485 uint16_t temperature_vrsoc;
486 uint16_t temperature_vrmem;
487
488 /* Utilization */
489 uint16_t average_gfx_activity;
490 uint16_t average_umc_activity; // memory controller
491 uint16_t average_mm_activity; // UVD or VCN
492
493 /* Power/Energy */
494 uint16_t average_socket_power;
495 uint64_t energy_accumulator;
496
497 /* Driver attached timestamp (in ns) */
498 uint64_t system_clock_counter;
499
500 /* Average clocks */
501 uint16_t average_gfxclk_frequency;
502 uint16_t average_socclk_frequency;
503 uint16_t average_uclk_frequency;
504 uint16_t average_vclk0_frequency;
505 uint16_t average_dclk0_frequency;
506 uint16_t average_vclk1_frequency;
507 uint16_t average_dclk1_frequency;
508
509 /* Current clocks */
510 uint16_t current_gfxclk;
511 uint16_t current_socclk;
512 uint16_t current_uclk;
513 uint16_t current_vclk0;
514 uint16_t current_dclk0;
515 uint16_t current_vclk1;
516 uint16_t current_dclk1;
517
518 /* Throttle status */
519 uint32_t throttle_status;
520
521 /* Fans */
522 uint16_t current_fan_speed;
523
524 /* Link width/speed */
525 uint16_t pcie_link_width;
526 uint16_t pcie_link_speed; // in 0.1 GT/s
527
528 uint16_t padding;
529
530 uint32_t gfx_activity_acc;
531 uint32_t mem_activity_acc;
532
533 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
534};
535
536struct gpu_metrics_v1_2 {
537 struct metrics_table_header common_header;
538
539 /* Temperature */
540 uint16_t temperature_edge;
541 uint16_t temperature_hotspot;
542 uint16_t temperature_mem;
543 uint16_t temperature_vrgfx;
544 uint16_t temperature_vrsoc;
545 uint16_t temperature_vrmem;
546
547 /* Utilization */
548 uint16_t average_gfx_activity;
549 uint16_t average_umc_activity; // memory controller
550 uint16_t average_mm_activity; // UVD or VCN
551
552 /* Power/Energy */
553 uint16_t average_socket_power;
554 uint64_t energy_accumulator;
555
556 /* Driver attached timestamp (in ns) */
557 uint64_t system_clock_counter;
558
559 /* Average clocks */
560 uint16_t average_gfxclk_frequency;
561 uint16_t average_socclk_frequency;
562 uint16_t average_uclk_frequency;
563 uint16_t average_vclk0_frequency;
564 uint16_t average_dclk0_frequency;
565 uint16_t average_vclk1_frequency;
566 uint16_t average_dclk1_frequency;
567
568 /* Current clocks */
569 uint16_t current_gfxclk;
570 uint16_t current_socclk;
571 uint16_t current_uclk;
572 uint16_t current_vclk0;
573 uint16_t current_dclk0;
574 uint16_t current_vclk1;
575 uint16_t current_dclk1;
576
577 /* Throttle status (ASIC dependent) */
578 uint32_t throttle_status;
579
580 /* Fans */
581 uint16_t current_fan_speed;
582
583 /* Link width/speed */
584 uint16_t pcie_link_width;
585 uint16_t pcie_link_speed; // in 0.1 GT/s
586
587 uint16_t padding;
588
589 uint32_t gfx_activity_acc;
590 uint32_t mem_activity_acc;
591
592 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
593
594 /* PMFW attached timestamp (10ns resolution) */
595 uint64_t firmware_timestamp;
596};
597
598struct gpu_metrics_v1_3 {
599 struct metrics_table_header common_header;
600
601 /* Temperature */
602 uint16_t temperature_edge;
603 uint16_t temperature_hotspot;
604 uint16_t temperature_mem;
605 uint16_t temperature_vrgfx;
606 uint16_t temperature_vrsoc;
607 uint16_t temperature_vrmem;
608
609 /* Utilization */
610 uint16_t average_gfx_activity;
611 uint16_t average_umc_activity; // memory controller
612 uint16_t average_mm_activity; // UVD or VCN
613
614 /* Power/Energy */
615 uint16_t average_socket_power;
616 uint64_t energy_accumulator;
617
618 /* Driver attached timestamp (in ns) */
619 uint64_t system_clock_counter;
620
621 /* Average clocks */
622 uint16_t average_gfxclk_frequency;
623 uint16_t average_socclk_frequency;
624 uint16_t average_uclk_frequency;
625 uint16_t average_vclk0_frequency;
626 uint16_t average_dclk0_frequency;
627 uint16_t average_vclk1_frequency;
628 uint16_t average_dclk1_frequency;
629
630 /* Current clocks */
631 uint16_t current_gfxclk;
632 uint16_t current_socclk;
633 uint16_t current_uclk;
634 uint16_t current_vclk0;
635 uint16_t current_dclk0;
636 uint16_t current_vclk1;
637 uint16_t current_dclk1;
638
639 /* Throttle status */
640 uint32_t throttle_status;
641
642 /* Fans */
643 uint16_t current_fan_speed;
644
645 /* Link width/speed */
646 uint16_t pcie_link_width;
647 uint16_t pcie_link_speed; // in 0.1 GT/s
648
649 uint16_t padding;
650
651 uint32_t gfx_activity_acc;
652 uint32_t mem_activity_acc;
653
654 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
655
656 /* PMFW attached timestamp (10ns resolution) */
657 uint64_t firmware_timestamp;
658
659 /* Voltage (mV) */
660 uint16_t voltage_soc;
661 uint16_t voltage_gfx;
662 uint16_t voltage_mem;
663
664 uint16_t padding1;
665
666 /* Throttle status (ASIC independent) */
667 uint64_t indep_throttle_status;
668};
669
670/*
671 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
672 * Use gpu_metrics_v2_1 or later instead.
673 */
674struct gpu_metrics_v2_0 {
675 struct metrics_table_header common_header;
676
677 /* Driver attached timestamp (in ns) */
678 uint64_t system_clock_counter;
679
680 /* Temperature */
681 uint16_t temperature_gfx; // gfx temperature on APUs
682 uint16_t temperature_soc; // soc temperature on APUs
683 uint16_t temperature_core[8]; // CPU core temperature on APUs
684 uint16_t temperature_l3[2];
685
686 /* Utilization */
687 uint16_t average_gfx_activity;
688 uint16_t average_mm_activity; // UVD or VCN
689
690 /* Power/Energy */
691 uint16_t average_socket_power; // dGPU + APU power on A + A platform
692 uint16_t average_cpu_power;
693 uint16_t average_soc_power;
694 uint16_t average_gfx_power;
695 uint16_t average_core_power[8]; // CPU core power on APUs
696
697 /* Average clocks */
698 uint16_t average_gfxclk_frequency;
699 uint16_t average_socclk_frequency;
700 uint16_t average_uclk_frequency;
701 uint16_t average_fclk_frequency;
702 uint16_t average_vclk_frequency;
703 uint16_t average_dclk_frequency;
704
705 /* Current clocks */
706 uint16_t current_gfxclk;
707 uint16_t current_socclk;
708 uint16_t current_uclk;
709 uint16_t current_fclk;
710 uint16_t current_vclk;
711 uint16_t current_dclk;
712 uint16_t current_coreclk[8]; // CPU core clocks
713 uint16_t current_l3clk[2];
714
715 /* Throttle status */
716 uint32_t throttle_status;
717
718 /* Fans */
719 uint16_t fan_pwm;
720
721 uint16_t padding;
722};
723
724struct gpu_metrics_v2_1 {
725 struct metrics_table_header common_header;
726
727 /* Temperature */
728 uint16_t temperature_gfx; // gfx temperature on APUs
729 uint16_t temperature_soc; // soc temperature on APUs
730 uint16_t temperature_core[8]; // CPU core temperature on APUs
731 uint16_t temperature_l3[2];
732
733 /* Utilization */
734 uint16_t average_gfx_activity;
735 uint16_t average_mm_activity; // UVD or VCN
736
737 /* Driver attached timestamp (in ns) */
738 uint64_t system_clock_counter;
739
740 /* Power/Energy */
741 uint16_t average_socket_power; // dGPU + APU power on A + A platform
742 uint16_t average_cpu_power;
743 uint16_t average_soc_power;
744 uint16_t average_gfx_power;
745 uint16_t average_core_power[8]; // CPU core power on APUs
746
747 /* Average clocks */
748 uint16_t average_gfxclk_frequency;
749 uint16_t average_socclk_frequency;
750 uint16_t average_uclk_frequency;
751 uint16_t average_fclk_frequency;
752 uint16_t average_vclk_frequency;
753 uint16_t average_dclk_frequency;
754
755 /* Current clocks */
756 uint16_t current_gfxclk;
757 uint16_t current_socclk;
758 uint16_t current_uclk;
759 uint16_t current_fclk;
760 uint16_t current_vclk;
761 uint16_t current_dclk;
762 uint16_t current_coreclk[8]; // CPU core clocks
763 uint16_t current_l3clk[2];
764
765 /* Throttle status */
766 uint32_t throttle_status;
767
768 /* Fans */
769 uint16_t fan_pwm;
770
771 uint16_t padding[3];
772};
773
774struct gpu_metrics_v2_2 {
775 struct metrics_table_header common_header;
776
777 /* Temperature */
778 uint16_t temperature_gfx; // gfx temperature on APUs
779 uint16_t temperature_soc; // soc temperature on APUs
780 uint16_t temperature_core[8]; // CPU core temperature on APUs
781 uint16_t temperature_l3[2];
782
783 /* Utilization */
784 uint16_t average_gfx_activity;
785 uint16_t average_mm_activity; // UVD or VCN
786
787 /* Driver attached timestamp (in ns) */
788 uint64_t system_clock_counter;
789
790 /* Power/Energy */
791 uint16_t average_socket_power; // dGPU + APU power on A + A platform
792 uint16_t average_cpu_power;
793 uint16_t average_soc_power;
794 uint16_t average_gfx_power;
795 uint16_t average_core_power[8]; // CPU core power on APUs
796
797 /* Average clocks */
798 uint16_t average_gfxclk_frequency;
799 uint16_t average_socclk_frequency;
800 uint16_t average_uclk_frequency;
801 uint16_t average_fclk_frequency;
802 uint16_t average_vclk_frequency;
803 uint16_t average_dclk_frequency;
804
805 /* Current clocks */
806 uint16_t current_gfxclk;
807 uint16_t current_socclk;
808 uint16_t current_uclk;
809 uint16_t current_fclk;
810 uint16_t current_vclk;
811 uint16_t current_dclk;
812 uint16_t current_coreclk[8]; // CPU core clocks
813 uint16_t current_l3clk[2];
814
815 /* Throttle status (ASIC dependent) */
816 uint32_t throttle_status;
817
818 /* Fans */
819 uint16_t fan_pwm;
820
821 uint16_t padding[3];
822
823 /* Throttle status (ASIC independent) */
824 uint64_t indep_throttle_status;
825};
826
827#endif