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Linux kernel mirror (for testing)
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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dc_features.h"
27#include "display_mode_enums.h"
28
29#ifndef __DISPLAY_MODE_STRUCTS_H__
30#define __DISPLAY_MODE_STRUCTS_H__
31
32typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
33typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
34typedef struct _vcs_dpi_ip_params_st ip_params_st;
35typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
36typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
37typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
38typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
39typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
40typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
41typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
42typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
43typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
44typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
45typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
46typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
47typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
48typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
49typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
50typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
51typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
52typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
53typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
54typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
55typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
56
57struct _vcs_dpi_voltage_scaling_st {
58 int state;
59 double dscclk_mhz;
60 double dcfclk_mhz;
61 double socclk_mhz;
62 double phyclk_d18_mhz;
63 double dram_speed_mts;
64 double fabricclk_mhz;
65 double dispclk_mhz;
66 double dram_bw_per_chan_gbps;
67 double phyclk_mhz;
68 double dppclk_mhz;
69 double dtbclk_mhz;
70};
71
72struct _vcs_dpi_soc_bounding_box_st {
73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
74 unsigned int num_states;
75 double sr_exit_time_us;
76 double sr_enter_plus_exit_time_us;
77 double sr_exit_z8_time_us;
78 double sr_enter_plus_exit_z8_time_us;
79 double urgent_latency_us;
80 double urgent_latency_pixel_data_only_us;
81 double urgent_latency_pixel_mixed_with_vm_data_us;
82 double urgent_latency_vm_data_only_us;
83 double writeback_latency_us;
84 double ideal_dram_bw_after_urgent_percent;
85 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
86 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
87 double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
88 double pct_ideal_sdp_bw_after_urgent;
89 double max_avg_sdp_bw_use_normal_percent;
90 double max_avg_dram_bw_use_normal_percent;
91 unsigned int max_request_size_bytes;
92 double downspread_percent;
93 double dram_page_open_time_ns;
94 double dram_rw_turnaround_time_ns;
95 double dram_return_buffer_per_channel_bytes;
96 double dram_channel_width_bytes;
97 double fabric_datapath_to_dcn_data_return_bytes;
98 double dcn_downspread_percent;
99 double dispclk_dppclk_vco_speed_mhz;
100 double dfs_vco_period_ps;
101 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
102 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
103 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
104 unsigned int round_trip_ping_latency_dcfclk_cycles;
105 unsigned int urgent_out_of_order_return_per_channel_bytes;
106 unsigned int channel_interleave_bytes;
107 unsigned int num_banks;
108 unsigned int num_chans;
109 unsigned int vmm_page_size_bytes;
110 unsigned int hostvm_min_page_size_bytes;
111 unsigned int gpuvm_min_page_size_bytes;
112 double dram_clock_change_latency_us;
113 double dummy_pstate_latency_us;
114 double writeback_dram_clock_change_latency_us;
115 unsigned int return_bus_width_bytes;
116 unsigned int voltage_override;
117 double xfc_bus_transport_time_us;
118 double xfc_xbuf_latency_tolerance_us;
119 int use_urgent_burst_bw;
120 double min_dcfclk;
121 bool do_urgent_latency_adjustment;
122 double urgent_latency_adjustment_fabric_clock_component_us;
123 double urgent_latency_adjustment_fabric_clock_reference_mhz;
124 bool disable_dram_clock_change_vactive_support;
125 bool allow_dram_clock_one_display_vactive;
126 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank;
127};
128
129struct _vcs_dpi_ip_params_st {
130 bool use_min_dcfclk;
131 bool clamp_min_dcfclk;
132 bool gpuvm_enable;
133 bool hostvm_enable;
134 bool dsc422_native_support;
135 unsigned int gpuvm_max_page_table_levels;
136 unsigned int hostvm_max_page_table_levels;
137 unsigned int hostvm_cached_page_table_levels;
138 unsigned int pte_group_size_bytes;
139 unsigned int max_inter_dcn_tile_repeaters;
140 unsigned int num_dsc;
141 unsigned int odm_capable;
142 unsigned int rob_buffer_size_kbytes;
143 unsigned int det_buffer_size_kbytes;
144 unsigned int min_comp_buffer_size_kbytes;
145 unsigned int dpte_buffer_size_in_pte_reqs_luma;
146 unsigned int dpte_buffer_size_in_pte_reqs_chroma;
147 unsigned int pde_proc_buffer_size_64k_reqs;
148 unsigned int dpp_output_buffer_pixels;
149 unsigned int opp_output_buffer_lines;
150 unsigned int pixel_chunk_size_kbytes;
151 unsigned char pte_enable;
152 unsigned int pte_chunk_size_kbytes;
153 unsigned int meta_chunk_size_kbytes;
154 unsigned int min_meta_chunk_size_bytes;
155 unsigned int writeback_chunk_size_kbytes;
156 unsigned int line_buffer_size_bits;
157 unsigned int max_line_buffer_lines;
158 unsigned int writeback_luma_buffer_size_kbytes;
159 unsigned int writeback_chroma_buffer_size_kbytes;
160 unsigned int writeback_chroma_line_buffer_width_pixels;
161
162 unsigned int writeback_interface_buffer_size_kbytes;
163 unsigned int writeback_line_buffer_buffer_size;
164
165 unsigned int writeback_10bpc420_supported;
166 double writeback_max_hscl_ratio;
167 double writeback_max_vscl_ratio;
168 double writeback_min_hscl_ratio;
169 double writeback_min_vscl_ratio;
170 unsigned int maximum_dsc_bits_per_component;
171 unsigned int writeback_max_hscl_taps;
172 unsigned int writeback_max_vscl_taps;
173 unsigned int writeback_line_buffer_luma_buffer_size;
174 unsigned int writeback_line_buffer_chroma_buffer_size;
175
176 unsigned int max_page_table_levels;
177 unsigned int max_num_dpp;
178 unsigned int max_num_otg;
179 unsigned int cursor_chunk_size;
180 unsigned int cursor_buffer_size;
181 unsigned int max_num_wb;
182 unsigned int max_dchub_pscl_bw_pix_per_clk;
183 unsigned int max_pscl_lb_bw_pix_per_clk;
184 unsigned int max_lb_vscl_bw_pix_per_clk;
185 unsigned int max_vscl_hscl_bw_pix_per_clk;
186 double max_hscl_ratio;
187 double max_vscl_ratio;
188 unsigned int hscl_mults;
189 unsigned int vscl_mults;
190 unsigned int max_hscl_taps;
191 unsigned int max_vscl_taps;
192 unsigned int xfc_supported;
193 unsigned int ptoi_supported;
194 unsigned int gfx7_compat_tiling_supported;
195
196 bool odm_combine_4to1_supported;
197 bool dynamic_metadata_vm_enabled;
198 unsigned int max_num_hdmi_frl_outputs;
199
200 unsigned int xfc_fill_constant_bytes;
201 double dispclk_ramp_margin_percent;
202 double xfc_fill_bw_overhead_percent;
203 double underscan_factor;
204 unsigned int min_vblank_lines;
205 unsigned int dppclk_delay_subtotal;
206 unsigned int dispclk_delay_subtotal;
207 double dcfclk_cstate_latency;
208 unsigned int dppclk_delay_scl;
209 unsigned int dppclk_delay_scl_lb_only;
210 unsigned int dppclk_delay_cnvc_formatter;
211 unsigned int dppclk_delay_cnvc_cursor;
212 unsigned int is_line_buffer_bpp_fixed;
213 unsigned int line_buffer_fixed_bpp;
214 unsigned int dcc_supported;
215 unsigned int config_return_buffer_size_in_kbytes;
216 unsigned int compressed_buffer_segment_size_in_kbytes;
217 unsigned int meta_fifo_size_in_kentries;
218 unsigned int zero_size_buffer_entries;
219 unsigned int compbuf_reserved_space_64b;
220 unsigned int compbuf_reserved_space_zs;
221
222 unsigned int IsLineBufferBppFixed;
223 unsigned int LineBufferFixedBpp;
224 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
225 unsigned int bug_forcing_LC_req_same_size_fixed;
226 unsigned int number_of_cursors;
227};
228
229struct _vcs_dpi_display_xfc_params_st {
230 double xfc_tslv_vready_offset_us;
231 double xfc_tslv_vupdate_width_us;
232 double xfc_tslv_vupdate_offset_us;
233 int xfc_slv_chunk_size_bytes;
234};
235
236struct _vcs_dpi_display_pipe_source_params_st {
237 int source_format;
238 double dcc_fraction_of_zs_req_luma;
239 double dcc_fraction_of_zs_req_chroma;
240 unsigned char dcc;
241 unsigned int dcc_rate;
242 unsigned int dcc_rate_chroma;
243 unsigned char dcc_use_global;
244 unsigned char vm;
245 bool unbounded_req_mode;
246 bool gpuvm; // gpuvm enabled
247 bool hostvm; // hostvm enabled
248 bool gpuvm_levels_force_en;
249 unsigned int gpuvm_levels_force;
250 bool hostvm_levels_force_en;
251 unsigned int hostvm_levels_force;
252 int source_scan;
253 int sw_mode;
254 int macro_tile_size;
255 unsigned int surface_width_y;
256 unsigned int surface_height_y;
257 unsigned int surface_width_c;
258 unsigned int surface_height_c;
259 unsigned int viewport_width;
260 unsigned int viewport_height;
261 unsigned int viewport_y_y;
262 unsigned int viewport_y_c;
263 unsigned int viewport_width_c;
264 unsigned int viewport_height_c;
265 unsigned int viewport_width_max;
266 unsigned int viewport_height_max;
267 unsigned int data_pitch;
268 unsigned int data_pitch_c;
269 unsigned int meta_pitch;
270 unsigned int meta_pitch_c;
271 unsigned int cur0_src_width;
272 int cur0_bpp;
273 unsigned int cur1_src_width;
274 int cur1_bpp;
275 int num_cursors;
276 unsigned char is_hsplit;
277 unsigned char dynamic_metadata_enable;
278 unsigned int dynamic_metadata_lines_before_active;
279 unsigned int dynamic_metadata_xmit_bytes;
280 unsigned int hsplit_grp;
281 unsigned char xfc_enable;
282 unsigned char xfc_slave;
283 unsigned char immediate_flip;
284 struct _vcs_dpi_display_xfc_params_st xfc_params;
285 //for vstartuplines calculation freesync
286 unsigned char v_total_min;
287 unsigned char v_total_max;
288};
289struct writeback_st {
290 int wb_src_height;
291 int wb_src_width;
292 int wb_dst_width;
293 int wb_dst_height;
294 int wb_pixel_format;
295 int wb_htaps_luma;
296 int wb_vtaps_luma;
297 int wb_htaps_chroma;
298 int wb_vtaps_chroma;
299 double wb_hratio;
300 double wb_vratio;
301};
302
303struct _vcs_dpi_display_output_params_st {
304 int dp_lanes;
305 double output_bpp;
306 unsigned int dsc_input_bpc;
307 int dsc_enable;
308 int wb_enable;
309 int num_active_wb;
310 int output_type;
311 int is_virtual;
312 int output_format;
313 int dsc_slices;
314 int max_audio_sample_rate;
315 struct writeback_st wb;
316};
317
318struct _vcs_dpi_scaler_ratio_depth_st {
319 double hscl_ratio;
320 double vscl_ratio;
321 double hscl_ratio_c;
322 double vscl_ratio_c;
323 double vinit;
324 double vinit_c;
325 double vinit_bot;
326 double vinit_bot_c;
327 int lb_depth;
328 int scl_enable;
329};
330
331struct _vcs_dpi_scaler_taps_st {
332 unsigned int htaps;
333 unsigned int vtaps;
334 unsigned int htaps_c;
335 unsigned int vtaps_c;
336};
337
338struct _vcs_dpi_display_pipe_dest_params_st {
339 unsigned int recout_width;
340 unsigned int recout_height;
341 unsigned int full_recout_width;
342 unsigned int full_recout_height;
343 unsigned int hblank_start;
344 unsigned int hblank_end;
345 unsigned int vblank_start;
346 unsigned int vblank_end;
347 unsigned int htotal;
348 unsigned int vtotal;
349 unsigned int vfront_porch;
350 unsigned int vactive;
351 unsigned int hactive;
352 unsigned int vstartup_start;
353 unsigned int vupdate_offset;
354 unsigned int vupdate_width;
355 unsigned int vready_offset;
356 unsigned char interlaced;
357 double pixel_rate_mhz;
358 unsigned char synchronized_vblank_all_planes;
359 unsigned char otg_inst;
360 unsigned int odm_combine;
361 unsigned char use_maximum_vstartup;
362 unsigned int vtotal_max;
363 unsigned int vtotal_min;
364};
365
366struct _vcs_dpi_display_pipe_params_st {
367 display_pipe_source_params_st src;
368 display_pipe_dest_params_st dest;
369 scaler_ratio_depth_st scale_ratio_depth;
370 scaler_taps_st scale_taps;
371};
372
373struct _vcs_dpi_display_clocks_and_cfg_st {
374 int voltage;
375 double dppclk_mhz;
376 double refclk_mhz;
377 double dispclk_mhz;
378 double dcfclk_mhz;
379 double socclk_mhz;
380};
381
382struct _vcs_dpi_display_e2e_pipe_params_st {
383 display_pipe_params_st pipe;
384 display_output_params_st dout;
385 display_clocks_and_cfg_st clks_cfg;
386};
387
388struct _vcs_dpi_display_data_rq_misc_params_st {
389 unsigned int full_swath_bytes;
390 unsigned int stored_swath_bytes;
391 unsigned int blk256_height;
392 unsigned int blk256_width;
393 unsigned int req_height;
394 unsigned int req_width;
395};
396
397struct _vcs_dpi_display_data_rq_sizing_params_st {
398 unsigned int chunk_bytes;
399 unsigned int min_chunk_bytes;
400 unsigned int meta_chunk_bytes;
401 unsigned int min_meta_chunk_bytes;
402 unsigned int mpte_group_bytes;
403 unsigned int dpte_group_bytes;
404};
405
406struct _vcs_dpi_display_data_rq_dlg_params_st {
407 unsigned int swath_width_ub;
408 unsigned int swath_height;
409 unsigned int req_per_swath_ub;
410 unsigned int meta_pte_bytes_per_frame_ub;
411 unsigned int dpte_req_per_row_ub;
412 unsigned int dpte_groups_per_row_ub;
413 unsigned int dpte_row_height;
414 unsigned int dpte_bytes_per_row_ub;
415 unsigned int meta_chunks_per_row_ub;
416 unsigned int meta_req_per_row_ub;
417 unsigned int meta_row_height;
418 unsigned int meta_bytes_per_row_ub;
419};
420
421struct _vcs_dpi_display_rq_dlg_params_st {
422 display_data_rq_dlg_params_st rq_l;
423 display_data_rq_dlg_params_st rq_c;
424};
425
426struct _vcs_dpi_display_rq_sizing_params_st {
427 display_data_rq_sizing_params_st rq_l;
428 display_data_rq_sizing_params_st rq_c;
429};
430
431struct _vcs_dpi_display_rq_misc_params_st {
432 display_data_rq_misc_params_st rq_l;
433 display_data_rq_misc_params_st rq_c;
434};
435
436struct _vcs_dpi_display_rq_params_st {
437 unsigned char yuv420;
438 unsigned char yuv420_10bpc;
439 unsigned char rgbe_alpha;
440 display_rq_misc_params_st misc;
441 display_rq_sizing_params_st sizing;
442 display_rq_dlg_params_st dlg;
443};
444
445struct _vcs_dpi_display_dlg_regs_st {
446 unsigned int refcyc_h_blank_end;
447 unsigned int dlg_vblank_end;
448 unsigned int min_dst_y_next_start;
449 unsigned int optimized_min_dst_y_next_start;
450 unsigned int optimized_min_dst_y_next_start_us;
451 unsigned int refcyc_per_htotal;
452 unsigned int refcyc_x_after_scaler;
453 unsigned int dst_y_after_scaler;
454 unsigned int dst_y_prefetch;
455 unsigned int dst_y_per_vm_vblank;
456 unsigned int dst_y_per_row_vblank;
457 unsigned int dst_y_per_vm_flip;
458 unsigned int dst_y_per_row_flip;
459 unsigned int ref_freq_to_pix_freq;
460 unsigned int vratio_prefetch;
461 unsigned int vratio_prefetch_c;
462 unsigned int refcyc_per_pte_group_vblank_l;
463 unsigned int refcyc_per_pte_group_vblank_c;
464 unsigned int refcyc_per_meta_chunk_vblank_l;
465 unsigned int refcyc_per_meta_chunk_vblank_c;
466 unsigned int refcyc_per_pte_group_flip_l;
467 unsigned int refcyc_per_pte_group_flip_c;
468 unsigned int refcyc_per_meta_chunk_flip_l;
469 unsigned int refcyc_per_meta_chunk_flip_c;
470 unsigned int dst_y_per_pte_row_nom_l;
471 unsigned int dst_y_per_pte_row_nom_c;
472 unsigned int refcyc_per_pte_group_nom_l;
473 unsigned int refcyc_per_pte_group_nom_c;
474 unsigned int dst_y_per_meta_row_nom_l;
475 unsigned int dst_y_per_meta_row_nom_c;
476 unsigned int refcyc_per_meta_chunk_nom_l;
477 unsigned int refcyc_per_meta_chunk_nom_c;
478 unsigned int refcyc_per_line_delivery_pre_l;
479 unsigned int refcyc_per_line_delivery_pre_c;
480 unsigned int refcyc_per_line_delivery_l;
481 unsigned int refcyc_per_line_delivery_c;
482 unsigned int chunk_hdl_adjust_cur0;
483 unsigned int chunk_hdl_adjust_cur1;
484 unsigned int vready_after_vcount0;
485 unsigned int dst_y_offset_cur0;
486 unsigned int dst_y_offset_cur1;
487 unsigned int xfc_reg_transfer_delay;
488 unsigned int xfc_reg_precharge_delay;
489 unsigned int xfc_reg_remote_surface_flip_latency;
490 unsigned int xfc_reg_prefetch_margin;
491 unsigned int dst_y_delta_drq_limit;
492 unsigned int refcyc_per_vm_group_vblank;
493 unsigned int refcyc_per_vm_group_flip;
494 unsigned int refcyc_per_vm_req_vblank;
495 unsigned int refcyc_per_vm_req_flip;
496 unsigned int refcyc_per_vm_dmdata;
497 unsigned int dmdata_dl_delta;
498};
499
500struct _vcs_dpi_display_ttu_regs_st {
501 unsigned int qos_level_low_wm;
502 unsigned int qos_level_high_wm;
503 unsigned int min_ttu_vblank;
504 unsigned int qos_level_flip;
505 unsigned int refcyc_per_req_delivery_l;
506 unsigned int refcyc_per_req_delivery_c;
507 unsigned int refcyc_per_req_delivery_cur0;
508 unsigned int refcyc_per_req_delivery_cur1;
509 unsigned int refcyc_per_req_delivery_pre_l;
510 unsigned int refcyc_per_req_delivery_pre_c;
511 unsigned int refcyc_per_req_delivery_pre_cur0;
512 unsigned int refcyc_per_req_delivery_pre_cur1;
513 unsigned int qos_level_fixed_l;
514 unsigned int qos_level_fixed_c;
515 unsigned int qos_level_fixed_cur0;
516 unsigned int qos_level_fixed_cur1;
517 unsigned int qos_ramp_disable_l;
518 unsigned int qos_ramp_disable_c;
519 unsigned int qos_ramp_disable_cur0;
520 unsigned int qos_ramp_disable_cur1;
521};
522
523struct _vcs_dpi_display_data_rq_regs_st {
524 unsigned int chunk_size;
525 unsigned int min_chunk_size;
526 unsigned int meta_chunk_size;
527 unsigned int min_meta_chunk_size;
528 unsigned int dpte_group_size;
529 unsigned int mpte_group_size;
530 unsigned int swath_height;
531 unsigned int pte_row_height_linear;
532};
533
534struct _vcs_dpi_display_rq_regs_st {
535 display_data_rq_regs_st rq_regs_l;
536 display_data_rq_regs_st rq_regs_c;
537 unsigned int drq_expansion_mode;
538 unsigned int prq_expansion_mode;
539 unsigned int mrq_expansion_mode;
540 unsigned int crq_expansion_mode;
541 unsigned int plane1_base_address;
542 unsigned int aperture_low_addr; // bits [47:18]
543 unsigned int aperture_high_addr; // bits [47:18]
544};
545
546struct _vcs_dpi_display_dlg_sys_params_st {
547 double t_mclk_wm_us;
548 double t_urg_wm_us;
549 double t_sr_wm_us;
550 double t_extra_us;
551 double mem_trip_us;
552 double deepsleep_dcfclk_mhz;
553 double total_flip_bw;
554 unsigned int total_flip_bytes;
555};
556
557struct _vcs_dpi_display_arb_params_st {
558 int max_req_outstanding;
559 int min_req_outstanding;
560 int sat_level_us;
561};
562
563#endif /*__DISPLAY_MODE_STRUCTS_H__*/