tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2/* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs.
3 *
4 * Copyright (C) 2017 Texas Instruments Inc.
5 */
6
7#include <linux/ethtool.h>
8#include <linux/etherdevice.h>
9#include <linux/kernel.h>
10#include <linux/mii.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/phy.h>
14#include <linux/netdevice.h>
15
16#define DP83822_PHY_ID 0x2000a240
17#define DP83825S_PHY_ID 0x2000a140
18#define DP83825I_PHY_ID 0x2000a150
19#define DP83825CM_PHY_ID 0x2000a160
20#define DP83825CS_PHY_ID 0x2000a170
21#define DP83826C_PHY_ID 0x2000a130
22#define DP83826NC_PHY_ID 0x2000a110
23
24#define DP83822_DEVADDR 0x1f
25
26#define MII_DP83822_CTRL_2 0x0a
27#define MII_DP83822_PHYSTS 0x10
28#define MII_DP83822_PHYSCR 0x11
29#define MII_DP83822_MISR1 0x12
30#define MII_DP83822_MISR2 0x13
31#define MII_DP83822_FCSCR 0x14
32#define MII_DP83822_RCSR 0x17
33#define MII_DP83822_RESET_CTRL 0x1f
34#define MII_DP83822_GENCFG 0x465
35#define MII_DP83822_SOR1 0x467
36
37/* GENCFG */
38#define DP83822_SIG_DET_LOW BIT(0)
39
40/* Control Register 2 bits */
41#define DP83822_FX_ENABLE BIT(14)
42
43#define DP83822_HW_RESET BIT(15)
44#define DP83822_SW_RESET BIT(14)
45
46/* PHY STS bits */
47#define DP83822_PHYSTS_DUPLEX BIT(2)
48#define DP83822_PHYSTS_10 BIT(1)
49#define DP83822_PHYSTS_LINK BIT(0)
50
51/* PHYSCR Register Fields */
52#define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
53#define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */
54
55/* MISR1 bits */
56#define DP83822_RX_ERR_HF_INT_EN BIT(0)
57#define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1)
58#define DP83822_ANEG_COMPLETE_INT_EN BIT(2)
59#define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3)
60#define DP83822_SPEED_CHANGED_INT_EN BIT(4)
61#define DP83822_LINK_STAT_INT_EN BIT(5)
62#define DP83822_ENERGY_DET_INT_EN BIT(6)
63#define DP83822_LINK_QUAL_INT_EN BIT(7)
64
65/* MISR2 bits */
66#define DP83822_JABBER_DET_INT_EN BIT(0)
67#define DP83822_WOL_PKT_INT_EN BIT(1)
68#define DP83822_SLEEP_MODE_INT_EN BIT(2)
69#define DP83822_MDI_XOVER_INT_EN BIT(3)
70#define DP83822_LB_FIFO_INT_EN BIT(4)
71#define DP83822_PAGE_RX_INT_EN BIT(5)
72#define DP83822_ANEG_ERR_INT_EN BIT(6)
73#define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7)
74
75/* INT_STAT1 bits */
76#define DP83822_WOL_INT_EN BIT(4)
77#define DP83822_WOL_INT_STAT BIT(12)
78
79#define MII_DP83822_RXSOP1 0x04a5
80#define MII_DP83822_RXSOP2 0x04a6
81#define MII_DP83822_RXSOP3 0x04a7
82
83/* WoL Registers */
84#define MII_DP83822_WOL_CFG 0x04a0
85#define MII_DP83822_WOL_STAT 0x04a1
86#define MII_DP83822_WOL_DA1 0x04a2
87#define MII_DP83822_WOL_DA2 0x04a3
88#define MII_DP83822_WOL_DA3 0x04a4
89
90/* WoL bits */
91#define DP83822_WOL_MAGIC_EN BIT(0)
92#define DP83822_WOL_SECURE_ON BIT(5)
93#define DP83822_WOL_EN BIT(7)
94#define DP83822_WOL_INDICATION_SEL BIT(8)
95#define DP83822_WOL_CLR_INDICATION BIT(11)
96
97/* RCSR bits */
98#define DP83822_RGMII_MODE_EN BIT(9)
99#define DP83822_RX_CLK_SHIFT BIT(12)
100#define DP83822_TX_CLK_SHIFT BIT(11)
101
102/* SOR1 mode */
103#define DP83822_STRAP_MODE1 0
104#define DP83822_STRAP_MODE2 BIT(0)
105#define DP83822_STRAP_MODE3 BIT(1)
106#define DP83822_STRAP_MODE4 GENMASK(1, 0)
107
108#define DP83822_COL_STRAP_MASK GENMASK(11, 10)
109#define DP83822_COL_SHIFT 10
110#define DP83822_RX_ER_STR_MASK GENMASK(9, 8)
111#define DP83822_RX_ER_SHIFT 8
112
113#define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \
114 ADVERTISED_FIBRE | \
115 ADVERTISED_Pause | ADVERTISED_Asym_Pause)
116
117struct dp83822_private {
118 bool fx_signal_det_low;
119 int fx_enabled;
120 u16 fx_sd_enable;
121};
122
123static int dp83822_set_wol(struct phy_device *phydev,
124 struct ethtool_wolinfo *wol)
125{
126 struct net_device *ndev = phydev->attached_dev;
127 u16 value;
128 const u8 *mac;
129
130 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
131 mac = (const u8 *)ndev->dev_addr;
132
133 if (!is_valid_ether_addr(mac))
134 return -EINVAL;
135
136 /* MAC addresses start with byte 5, but stored in mac[0].
137 * 822 PHYs store bytes 4|5, 2|3, 0|1
138 */
139 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,
140 (mac[1] << 8) | mac[0]);
141 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,
142 (mac[3] << 8) | mac[2]);
143 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,
144 (mac[5] << 8) | mac[4]);
145
146 value = phy_read_mmd(phydev, DP83822_DEVADDR,
147 MII_DP83822_WOL_CFG);
148 if (wol->wolopts & WAKE_MAGIC)
149 value |= DP83822_WOL_MAGIC_EN;
150 else
151 value &= ~DP83822_WOL_MAGIC_EN;
152
153 if (wol->wolopts & WAKE_MAGICSECURE) {
154 phy_write_mmd(phydev, DP83822_DEVADDR,
155 MII_DP83822_RXSOP1,
156 (wol->sopass[1] << 8) | wol->sopass[0]);
157 phy_write_mmd(phydev, DP83822_DEVADDR,
158 MII_DP83822_RXSOP2,
159 (wol->sopass[3] << 8) | wol->sopass[2]);
160 phy_write_mmd(phydev, DP83822_DEVADDR,
161 MII_DP83822_RXSOP3,
162 (wol->sopass[5] << 8) | wol->sopass[4]);
163 value |= DP83822_WOL_SECURE_ON;
164 } else {
165 value &= ~DP83822_WOL_SECURE_ON;
166 }
167
168 /* Clear any pending WoL interrupt */
169 phy_read(phydev, MII_DP83822_MISR2);
170
171 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL |
172 DP83822_WOL_CLR_INDICATION;
173
174 return phy_write_mmd(phydev, DP83822_DEVADDR,
175 MII_DP83822_WOL_CFG, value);
176 } else {
177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
178 MII_DP83822_WOL_CFG, DP83822_WOL_EN);
179 }
180}
181
182static void dp83822_get_wol(struct phy_device *phydev,
183 struct ethtool_wolinfo *wol)
184{
185 int value;
186 u16 sopass_val;
187
188 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
189 wol->wolopts = 0;
190
191 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
192
193 if (value & DP83822_WOL_MAGIC_EN)
194 wol->wolopts |= WAKE_MAGIC;
195
196 if (value & DP83822_WOL_SECURE_ON) {
197 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
198 MII_DP83822_RXSOP1);
199 wol->sopass[0] = (sopass_val & 0xff);
200 wol->sopass[1] = (sopass_val >> 8);
201
202 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
203 MII_DP83822_RXSOP2);
204 wol->sopass[2] = (sopass_val & 0xff);
205 wol->sopass[3] = (sopass_val >> 8);
206
207 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,
208 MII_DP83822_RXSOP3);
209 wol->sopass[4] = (sopass_val & 0xff);
210 wol->sopass[5] = (sopass_val >> 8);
211
212 wol->wolopts |= WAKE_MAGICSECURE;
213 }
214
215 /* WoL is not enabled so set wolopts to 0 */
216 if (!(value & DP83822_WOL_EN))
217 wol->wolopts = 0;
218}
219
220static int dp83822_config_intr(struct phy_device *phydev)
221{
222 struct dp83822_private *dp83822 = phydev->priv;
223 int misr_status;
224 int physcr_status;
225 int err;
226
227 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
228 misr_status = phy_read(phydev, MII_DP83822_MISR1);
229 if (misr_status < 0)
230 return misr_status;
231
232 misr_status |= (DP83822_RX_ERR_HF_INT_EN |
233 DP83822_FALSE_CARRIER_HF_INT_EN |
234 DP83822_LINK_STAT_INT_EN |
235 DP83822_ENERGY_DET_INT_EN |
236 DP83822_LINK_QUAL_INT_EN);
237
238 if (!dp83822->fx_enabled)
239 misr_status |= DP83822_ANEG_COMPLETE_INT_EN |
240 DP83822_DUP_MODE_CHANGE_INT_EN |
241 DP83822_SPEED_CHANGED_INT_EN;
242
243
244 err = phy_write(phydev, MII_DP83822_MISR1, misr_status);
245 if (err < 0)
246 return err;
247
248 misr_status = phy_read(phydev, MII_DP83822_MISR2);
249 if (misr_status < 0)
250 return misr_status;
251
252 misr_status |= (DP83822_JABBER_DET_INT_EN |
253 DP83822_SLEEP_MODE_INT_EN |
254 DP83822_LB_FIFO_INT_EN |
255 DP83822_PAGE_RX_INT_EN |
256 DP83822_EEE_ERROR_CHANGE_INT_EN);
257
258 if (!dp83822->fx_enabled)
259 misr_status |= DP83822_MDI_XOVER_INT_EN |
260 DP83822_ANEG_ERR_INT_EN |
261 DP83822_WOL_PKT_INT_EN;
262
263 err = phy_write(phydev, MII_DP83822_MISR2, misr_status);
264 if (err < 0)
265 return err;
266
267 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
268 if (physcr_status < 0)
269 return physcr_status;
270
271 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN;
272
273 } else {
274 err = phy_write(phydev, MII_DP83822_MISR1, 0);
275 if (err < 0)
276 return err;
277
278 err = phy_write(phydev, MII_DP83822_MISR2, 0);
279 if (err < 0)
280 return err;
281
282 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR);
283 if (physcr_status < 0)
284 return physcr_status;
285
286 physcr_status &= ~DP83822_PHYSCR_INTEN;
287 }
288
289 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
290}
291
292static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev)
293{
294 bool trigger_machine = false;
295 int irq_status;
296
297 /* The MISR1 and MISR2 registers are holding the interrupt status in
298 * the upper half (15:8), while the lower half (7:0) is used for
299 * controlling the interrupt enable state of those individual interrupt
300 * sources. To determine the possible interrupt sources, just read the
301 * MISR* register and use it directly to know which interrupts have
302 * been enabled previously or not.
303 */
304 irq_status = phy_read(phydev, MII_DP83822_MISR1);
305 if (irq_status < 0) {
306 phy_error(phydev);
307 return IRQ_NONE;
308 }
309 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
310 trigger_machine = true;
311
312 irq_status = phy_read(phydev, MII_DP83822_MISR2);
313 if (irq_status < 0) {
314 phy_error(phydev);
315 return IRQ_NONE;
316 }
317 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
318 trigger_machine = true;
319
320 if (!trigger_machine)
321 return IRQ_NONE;
322
323 phy_trigger_machine(phydev);
324
325 return IRQ_HANDLED;
326}
327
328static int dp8382x_disable_wol(struct phy_device *phydev)
329{
330 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,
331 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
332 DP83822_WOL_SECURE_ON);
333}
334
335static int dp83822_read_status(struct phy_device *phydev)
336{
337 struct dp83822_private *dp83822 = phydev->priv;
338 int status = phy_read(phydev, MII_DP83822_PHYSTS);
339 int ctrl2;
340 int ret;
341
342 if (dp83822->fx_enabled) {
343 if (status & DP83822_PHYSTS_LINK) {
344 phydev->speed = SPEED_UNKNOWN;
345 phydev->duplex = DUPLEX_UNKNOWN;
346 } else {
347 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2);
348 if (ctrl2 < 0)
349 return ctrl2;
350
351 if (!(ctrl2 & DP83822_FX_ENABLE)) {
352 ret = phy_write(phydev, MII_DP83822_CTRL_2,
353 DP83822_FX_ENABLE | ctrl2);
354 if (ret < 0)
355 return ret;
356 }
357 }
358 }
359
360 ret = genphy_read_status(phydev);
361 if (ret)
362 return ret;
363
364 if (status < 0)
365 return status;
366
367 if (status & DP83822_PHYSTS_DUPLEX)
368 phydev->duplex = DUPLEX_FULL;
369 else
370 phydev->duplex = DUPLEX_HALF;
371
372 if (status & DP83822_PHYSTS_10)
373 phydev->speed = SPEED_10;
374 else
375 phydev->speed = SPEED_100;
376
377 return 0;
378}
379
380static int dp83822_config_init(struct phy_device *phydev)
381{
382 struct dp83822_private *dp83822 = phydev->priv;
383 struct device *dev = &phydev->mdio.dev;
384 int rgmii_delay;
385 s32 rx_int_delay;
386 s32 tx_int_delay;
387 int err = 0;
388 int bmcr;
389
390 if (phy_interface_is_rgmii(phydev)) {
391 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
392 true);
393
394 if (rx_int_delay <= 0)
395 rgmii_delay = 0;
396 else
397 rgmii_delay = DP83822_RX_CLK_SHIFT;
398
399 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
400 false);
401 if (tx_int_delay <= 0)
402 rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
403 else
404 rgmii_delay |= DP83822_TX_CLK_SHIFT;
405
406 if (rgmii_delay) {
407 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
408 MII_DP83822_RCSR, rgmii_delay);
409 if (err)
410 return err;
411 }
412
413 phy_set_bits_mmd(phydev, DP83822_DEVADDR,
414 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
415 } else {
416 phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
417 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
418 }
419
420 if (dp83822->fx_enabled) {
421 err = phy_modify(phydev, MII_DP83822_CTRL_2,
422 DP83822_FX_ENABLE, 1);
423 if (err < 0)
424 return err;
425
426 /* Only allow advertising what this PHY supports */
427 linkmode_and(phydev->advertising, phydev->advertising,
428 phydev->supported);
429
430 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
431 phydev->supported);
432 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
433 phydev->advertising);
434 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
435 phydev->supported);
436 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
437 phydev->supported);
438 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
439 phydev->advertising);
440 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
441 phydev->advertising);
442
443 /* Auto neg is not supported in fiber mode */
444 bmcr = phy_read(phydev, MII_BMCR);
445 if (bmcr < 0)
446 return bmcr;
447
448 if (bmcr & BMCR_ANENABLE) {
449 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
450 if (err < 0)
451 return err;
452 }
453 phydev->autoneg = AUTONEG_DISABLE;
454 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
455 phydev->supported);
456 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
457 phydev->advertising);
458
459 /* Setup fiber advertisement */
460 err = phy_modify_changed(phydev, MII_ADVERTISE,
461 MII_DP83822_FIBER_ADVERTISE,
462 MII_DP83822_FIBER_ADVERTISE);
463
464 if (err < 0)
465 return err;
466
467 if (dp83822->fx_signal_det_low) {
468 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
469 MII_DP83822_GENCFG,
470 DP83822_SIG_DET_LOW);
471 if (err)
472 return err;
473 }
474 }
475 return dp8382x_disable_wol(phydev);
476}
477
478static int dp8382x_config_init(struct phy_device *phydev)
479{
480 return dp8382x_disable_wol(phydev);
481}
482
483static int dp83822_phy_reset(struct phy_device *phydev)
484{
485 int err;
486
487 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET);
488 if (err < 0)
489 return err;
490
491 return phydev->drv->config_init(phydev);
492}
493
494#ifdef CONFIG_OF_MDIO
495static int dp83822_of_init(struct phy_device *phydev)
496{
497 struct dp83822_private *dp83822 = phydev->priv;
498 struct device *dev = &phydev->mdio.dev;
499
500 /* Signal detection for the PHY is only enabled if the FX_EN and the
501 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
502 * is strapped otherwise signal detection is disabled for the PHY.
503 */
504 if (dp83822->fx_enabled && dp83822->fx_sd_enable)
505 dp83822->fx_signal_det_low = device_property_present(dev,
506 "ti,link-loss-low");
507 if (!dp83822->fx_enabled)
508 dp83822->fx_enabled = device_property_present(dev,
509 "ti,fiber-mode");
510
511 return 0;
512}
513#else
514static int dp83822_of_init(struct phy_device *phydev)
515{
516 return 0;
517}
518#endif /* CONFIG_OF_MDIO */
519
520static int dp83822_read_straps(struct phy_device *phydev)
521{
522 struct dp83822_private *dp83822 = phydev->priv;
523 int fx_enabled, fx_sd_enable;
524 int val;
525
526 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
527 if (val < 0)
528 return val;
529
530 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT;
531 if (fx_enabled == DP83822_STRAP_MODE2 ||
532 fx_enabled == DP83822_STRAP_MODE3)
533 dp83822->fx_enabled = 1;
534
535 if (dp83822->fx_enabled) {
536 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT;
537 if (fx_sd_enable == DP83822_STRAP_MODE3 ||
538 fx_sd_enable == DP83822_STRAP_MODE4)
539 dp83822->fx_sd_enable = 1;
540 }
541
542 return 0;
543}
544
545static int dp83822_probe(struct phy_device *phydev)
546{
547 struct dp83822_private *dp83822;
548 int ret;
549
550 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
551 GFP_KERNEL);
552 if (!dp83822)
553 return -ENOMEM;
554
555 phydev->priv = dp83822;
556
557 ret = dp83822_read_straps(phydev);
558 if (ret)
559 return ret;
560
561 dp83822_of_init(phydev);
562
563 if (dp83822->fx_enabled)
564 phydev->port = PORT_FIBRE;
565
566 return 0;
567}
568
569static int dp83822_suspend(struct phy_device *phydev)
570{
571 int value;
572
573 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
574
575 if (!(value & DP83822_WOL_EN))
576 genphy_suspend(phydev);
577
578 return 0;
579}
580
581static int dp83822_resume(struct phy_device *phydev)
582{
583 int value;
584
585 genphy_resume(phydev);
586
587 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);
588
589 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |
590 DP83822_WOL_CLR_INDICATION);
591
592 return 0;
593}
594
595#define DP83822_PHY_DRIVER(_id, _name) \
596 { \
597 PHY_ID_MATCH_MODEL(_id), \
598 .name = (_name), \
599 /* PHY_BASIC_FEATURES */ \
600 .probe = dp83822_probe, \
601 .soft_reset = dp83822_phy_reset, \
602 .config_init = dp83822_config_init, \
603 .read_status = dp83822_read_status, \
604 .get_wol = dp83822_get_wol, \
605 .set_wol = dp83822_set_wol, \
606 .config_intr = dp83822_config_intr, \
607 .handle_interrupt = dp83822_handle_interrupt, \
608 .suspend = dp83822_suspend, \
609 .resume = dp83822_resume, \
610 }
611
612#define DP8382X_PHY_DRIVER(_id, _name) \
613 { \
614 PHY_ID_MATCH_MODEL(_id), \
615 .name = (_name), \
616 /* PHY_BASIC_FEATURES */ \
617 .soft_reset = dp83822_phy_reset, \
618 .config_init = dp8382x_config_init, \
619 .get_wol = dp83822_get_wol, \
620 .set_wol = dp83822_set_wol, \
621 .config_intr = dp83822_config_intr, \
622 .handle_interrupt = dp83822_handle_interrupt, \
623 .suspend = dp83822_suspend, \
624 .resume = dp83822_resume, \
625 }
626
627static struct phy_driver dp83822_driver[] = {
628 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
629 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
630 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
631 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
632 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
633 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
634 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
635};
636module_phy_driver(dp83822_driver);
637
638static struct mdio_device_id __maybe_unused dp83822_tbl[] = {
639 { DP83822_PHY_ID, 0xfffffff0 },
640 { DP83825I_PHY_ID, 0xfffffff0 },
641 { DP83826C_PHY_ID, 0xfffffff0 },
642 { DP83826NC_PHY_ID, 0xfffffff0 },
643 { DP83825S_PHY_ID, 0xfffffff0 },
644 { DP83825CM_PHY_ID, 0xfffffff0 },
645 { DP83825CS_PHY_ID, 0xfffffff0 },
646 { },
647};
648MODULE_DEVICE_TABLE(mdio, dp83822_tbl);
649
650MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver");
651MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
652MODULE_LICENSE("GPL v2");