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linux
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES && (EDAC=y)
58 select UEFI_CPER
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
78config EDAC_AMD64
79 tristate "AMD64 (Opteron, Athlon64)"
80 depends on AMD_NB && EDAC_DECODE_MCE
81 help
82 Support for error detection and correction of DRAM ECC errors on
83 the AMD64 families (>= K8) of memory controllers.
84
85 When EDAC_DEBUG is enabled, hardware error injection facilities
86 through sysfs are available:
87
88 AMD CPUs up to and excluding family 0x17 provide for Memory
89 Error Injection into the ECC detection circuits. The amd64_edac
90 module allows the operator/user to inject Uncorrectable and
91 Correctable errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
102
103config EDAC_AL_MC
104 tristate "Amazon's Annapurna Lab Memory Controller"
105 depends on (ARCH_ALPINE || COMPILE_TEST)
106 help
107 Support for error detection and correction for Amazon's Annapurna
108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
109
110config EDAC_AMD76X
111 tristate "AMD 76x (760, 762, 768)"
112 depends on PCI && X86_32
113 help
114 Support for error detection and correction on the AMD 76x
115 series of chipsets used with the Athlon processor.
116
117config EDAC_E7XXX
118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
119 depends on PCI && X86_32
120 help
121 Support for error detection and correction on the Intel
122 E7205, E7500, E7501 and E7505 server chipsets.
123
124config EDAC_E752X
125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
126 depends on PCI && X86
127 help
128 Support for error detection and correction on the Intel
129 E7520, E7525, E7320 server chipsets.
130
131config EDAC_I82443BXGX
132 tristate "Intel 82443BX/GX (440BX/GX)"
133 depends on PCI && X86_32
134 depends on BROKEN
135 help
136 Support for error detection and correction on the Intel
137 82443BX/GX memory controllers (440BX/GX chipsets).
138
139config EDAC_I82875P
140 tristate "Intel 82875p (D82875P, E7210)"
141 depends on PCI && X86_32
142 help
143 Support for error detection and correction on the Intel
144 DP82785P and E7210 server chipsets.
145
146config EDAC_I82975X
147 tristate "Intel 82975x (D82975x)"
148 depends on PCI && X86
149 help
150 Support for error detection and correction on the Intel
151 DP82975x server chipsets.
152
153config EDAC_I3000
154 tristate "Intel 3000/3010"
155 depends on PCI && X86
156 help
157 Support for error detection and correction on the Intel
158 3000 and 3010 server chipsets.
159
160config EDAC_I3200
161 tristate "Intel 3200"
162 depends on PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 3200 and 3210 server chipsets.
166
167config EDAC_IE31200
168 tristate "Intel e312xx"
169 depends on PCI && X86
170 help
171 Support for error detection and correction on the Intel
172 E3-1200 based DRAM controllers.
173
174config EDAC_X38
175 tristate "Intel X38"
176 depends on PCI && X86
177 help
178 Support for error detection and correction on the Intel
179 X38 server chipsets.
180
181config EDAC_I5400
182 tristate "Intel 5400 (Seaburg) chipsets"
183 depends on PCI && X86
184 help
185 Support for error detection and correction the Intel
186 i5400 MCH chipset (Seaburg).
187
188config EDAC_I7CORE
189 tristate "Intel i7 Core (Nehalem) processors"
190 depends on PCI && X86 && X86_MCE_INTEL
191 help
192 Support for error detection and correction the Intel
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
195 and Xeon 55xx processors.
196
197config EDAC_I82860
198 tristate "Intel 82860"
199 depends on PCI && X86_32
200 help
201 Support for error detection and correction on the Intel
202 82860 chipset.
203
204config EDAC_R82600
205 tristate "Radisys 82600 embedded chipset"
206 depends on PCI && X86_32
207 help
208 Support for error detection and correction on the Radisys
209 82600 embedded chipset.
210
211config EDAC_I5000
212 tristate "Intel Greencreek/Blackford chipset"
213 depends on X86 && PCI
214 help
215 Support for error detection and correction the Intel
216 Greekcreek/Blackford chipsets.
217
218config EDAC_I5100
219 tristate "Intel San Clemente MCH"
220 depends on X86 && PCI
221 help
222 Support for error detection and correction the Intel
223 San Clemente MCH.
224
225config EDAC_I7300
226 tristate "Intel Clarksboro MCH"
227 depends on X86 && PCI
228 help
229 Support for error detection and correction the Intel
230 Clarksboro MCH (Intel 7300 chipset).
231
232config EDAC_SBRIDGE
233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
235 help
236 Support for error detection and correction the Intel
237 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
238
239config EDAC_SKX
240 tristate "Intel Skylake server Integrated MC"
241 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
242 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
243 select DMI
244 select ACPI_ADXL
245 help
246 Support for error detection and correction the Intel
247 Skylake server Integrated Memory Controllers. If your
248 system has non-volatile DIMMs you should also manually
249 select CONFIG_ACPI_NFIT.
250
251config EDAC_I10NM
252 tristate "Intel 10nm server Integrated MC"
253 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
254 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
255 select DMI
256 select ACPI_ADXL
257 help
258 Support for error detection and correction the Intel
259 10nm server Integrated Memory Controllers. If your
260 system has non-volatile DIMMs you should also manually
261 select CONFIG_ACPI_NFIT.
262
263config EDAC_PND2
264 tristate "Intel Pondicherry2"
265 depends on PCI && X86_64 && X86_MCE_INTEL
266 help
267 Support for error detection and correction on the Intel
268 Pondicherry2 Integrated Memory Controller. This SoC IP is
269 first used on the Apollo Lake platform and Denverton
270 micro-server but may appear on others in the future.
271
272config EDAC_IGEN6
273 tristate "Intel client SoC Integrated MC"
274 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
275 depends on X86_64 && X86_MCE_INTEL
276 help
277 Support for error detection and correction on the Intel
278 client SoC Integrated Memory Controller using In-Band ECC IP.
279 This In-Band ECC is first used on the Elkhart Lake SoC but
280 may appear on others in the future.
281
282config EDAC_MPC85XX
283 bool "Freescale MPC83xx / MPC85xx"
284 depends on FSL_SOC && EDAC=y
285 help
286 Support for error detection and correction on the Freescale
287 MPC8349, MPC8560, MPC8540, MPC8548, T4240
288
289config EDAC_LAYERSCAPE
290 tristate "Freescale Layerscape DDR"
291 depends on ARCH_LAYERSCAPE || SOC_LS1021A
292 help
293 Support for error detection and correction on Freescale memory
294 controllers on Layerscape SoCs.
295
296config EDAC_PASEMI
297 tristate "PA Semi PWRficient"
298 depends on PPC_PASEMI && PCI
299 help
300 Support for error detection and correction on PA Semi
301 PWRficient.
302
303config EDAC_CELL
304 tristate "Cell Broadband Engine memory controller"
305 depends on PPC_CELL_COMMON
306 help
307 Support for error detection and correction on the
308 Cell Broadband Engine internal memory controller
309 on platform without a hypervisor
310
311config EDAC_PPC4XX
312 tristate "PPC4xx IBM DDR2 Memory Controller"
313 depends on 4xx
314 help
315 This enables support for EDAC on the ECC memory used
316 with the IBM DDR2 memory controller found in various
317 PowerPC 4xx embedded processors such as the 405EX[r],
318 440SP, 440SPe, 460EX, 460GT and 460SX.
319
320config EDAC_AMD8131
321 tristate "AMD8131 HyperTransport PCI-X Tunnel"
322 depends on PCI && PPC_MAPLE
323 help
324 Support for error detection and correction on the
325 AMD8131 HyperTransport PCI-X Tunnel chip.
326 Note, add more Kconfig dependency if it's adopted
327 on some machine other than Maple.
328
329config EDAC_AMD8111
330 tristate "AMD8111 HyperTransport I/O Hub"
331 depends on PCI && PPC_MAPLE
332 help
333 Support for error detection and correction on the
334 AMD8111 HyperTransport I/O Hub chip.
335 Note, add more Kconfig dependency if it's adopted
336 on some machine other than Maple.
337
338config EDAC_CPC925
339 tristate "IBM CPC925 Memory Controller (PPC970FX)"
340 depends on PPC64
341 help
342 Support for error detection and correction on the
343 IBM CPC925 Bridge and Memory Controller, which is
344 a companion chip to the PowerPC 970 family of
345 processors.
346
347config EDAC_HIGHBANK_MC
348 tristate "Highbank Memory Controller"
349 depends on ARCH_HIGHBANK
350 help
351 Support for error detection and correction on the
352 Calxeda Highbank memory controller.
353
354config EDAC_HIGHBANK_L2
355 tristate "Highbank L2 Cache"
356 depends on ARCH_HIGHBANK
357 help
358 Support for error detection and correction on the
359 Calxeda Highbank memory controller.
360
361config EDAC_OCTEON_PC
362 tristate "Cavium Octeon Primary Caches"
363 depends on CPU_CAVIUM_OCTEON
364 help
365 Support for error detection and correction on the primary caches of
366 the cnMIPS cores of Cavium Octeon family SOCs.
367
368config EDAC_OCTEON_L2C
369 tristate "Cavium Octeon Secondary Caches (L2C)"
370 depends on CAVIUM_OCTEON_SOC
371 help
372 Support for error detection and correction on the
373 Cavium Octeon family of SOCs.
374
375config EDAC_OCTEON_LMC
376 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
377 depends on CAVIUM_OCTEON_SOC
378 help
379 Support for error detection and correction on the
380 Cavium Octeon family of SOCs.
381
382config EDAC_OCTEON_PCI
383 tristate "Cavium Octeon PCI Controller"
384 depends on PCI && CAVIUM_OCTEON_SOC
385 help
386 Support for error detection and correction on the
387 Cavium Octeon family of SOCs.
388
389config EDAC_THUNDERX
390 tristate "Cavium ThunderX EDAC"
391 depends on ARM64
392 depends on PCI
393 help
394 Support for error detection and correction on the
395 Cavium ThunderX memory controllers (LMC), Cache
396 Coherent Processor Interconnect (CCPI) and L2 cache
397 blocks (TAD, CBC, MCI).
398
399config EDAC_ALTERA
400 bool "Altera SOCFPGA ECC"
401 depends on EDAC=y && ARCH_INTEL_SOCFPGA
402 help
403 Support for error detection and correction on the
404 Altera SOCs. This is the global enable for the
405 various Altera peripherals.
406
407config EDAC_ALTERA_SDRAM
408 bool "Altera SDRAM ECC"
409 depends on EDAC_ALTERA=y
410 help
411 Support for error detection and correction on the
412 Altera SDRAM Memory for Altera SoCs. Note that the
413 preloader must initialize the SDRAM before loading
414 the kernel.
415
416config EDAC_ALTERA_L2C
417 bool "Altera L2 Cache ECC"
418 depends on EDAC_ALTERA=y && CACHE_L2X0
419 help
420 Support for error detection and correction on the
421 Altera L2 cache Memory for Altera SoCs. This option
422 requires L2 cache.
423
424config EDAC_ALTERA_OCRAM
425 bool "Altera On-Chip RAM ECC"
426 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
427 help
428 Support for error detection and correction on the
429 Altera On-Chip RAM Memory for Altera SoCs.
430
431config EDAC_ALTERA_ETHERNET
432 bool "Altera Ethernet FIFO ECC"
433 depends on EDAC_ALTERA=y
434 help
435 Support for error detection and correction on the
436 Altera Ethernet FIFO Memory for Altera SoCs.
437
438config EDAC_ALTERA_NAND
439 bool "Altera NAND FIFO ECC"
440 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
441 help
442 Support for error detection and correction on the
443 Altera NAND FIFO Memory for Altera SoCs.
444
445config EDAC_ALTERA_DMA
446 bool "Altera DMA FIFO ECC"
447 depends on EDAC_ALTERA=y && PL330_DMA=y
448 help
449 Support for error detection and correction on the
450 Altera DMA FIFO Memory for Altera SoCs.
451
452config EDAC_ALTERA_USB
453 bool "Altera USB FIFO ECC"
454 depends on EDAC_ALTERA=y && USB_DWC2
455 help
456 Support for error detection and correction on the
457 Altera USB FIFO Memory for Altera SoCs.
458
459config EDAC_ALTERA_QSPI
460 bool "Altera QSPI FIFO ECC"
461 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
462 help
463 Support for error detection and correction on the
464 Altera QSPI FIFO Memory for Altera SoCs.
465
466config EDAC_ALTERA_SDMMC
467 bool "Altera SDMMC FIFO ECC"
468 depends on EDAC_ALTERA=y && MMC_DW
469 help
470 Support for error detection and correction on the
471 Altera SDMMC FIFO Memory for Altera SoCs.
472
473config EDAC_SIFIVE
474 bool "Sifive platform EDAC driver"
475 depends on EDAC=y && SIFIVE_L2
476 help
477 Support for error detection and correction on the SiFive SoCs.
478
479config EDAC_ARMADA_XP
480 bool "Marvell Armada XP DDR and L2 Cache ECC"
481 depends on MACH_MVEBU_V7
482 help
483 Support for error correction and detection on the Marvell Aramada XP
484 DDR RAM and L2 cache controllers.
485
486config EDAC_SYNOPSYS
487 tristate "Synopsys DDR Memory Controller"
488 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
489 help
490 Support for error detection and correction on the Synopsys DDR
491 memory controller.
492
493config EDAC_XGENE
494 tristate "APM X-Gene SoC"
495 depends on (ARM64 || COMPILE_TEST)
496 help
497 Support for error detection and correction on the
498 APM X-Gene family of SOCs.
499
500config EDAC_TI
501 tristate "Texas Instruments DDR3 ECC Controller"
502 depends on ARCH_KEYSTONE || SOC_DRA7XX
503 help
504 Support for error detection and correction on the TI SoCs.
505
506config EDAC_QCOM
507 tristate "QCOM EDAC Controller"
508 depends on ARCH_QCOM && QCOM_LLCC
509 help
510 Support for error detection and correction on the
511 Qualcomm Technologies, Inc. SoCs.
512
513 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
514 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
515 of Tag RAM and Data RAM.
516
517 For debugging issues having to do with stability and overall system
518 health, you should probably say 'Y' here.
519
520config EDAC_ASPEED
521 tristate "Aspeed AST BMC SoC"
522 depends on ARCH_ASPEED
523 help
524 Support for error detection and correction on the Aspeed AST BMC SoC.
525
526 First, ECC must be configured in the bootloader. Then, this driver
527 will expose error counters via the EDAC kernel framework.
528
529config EDAC_BLUEFIELD
530 tristate "Mellanox BlueField Memory ECC"
531 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
532 help
533 Support for error detection and correction on the
534 Mellanox BlueField SoCs.
535
536config EDAC_DMC520
537 tristate "ARM DMC-520 ECC"
538 depends on ARM64
539 help
540 Support for error detection and correction on the
541 SoCs with ARM DMC-520 DRAM controller.
542
543endif # EDAC