tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v4_3.h"
26
27#include "nbio/nbio_4_3_0_offset.h"
28#include "nbio/nbio_4_3_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev)
32{
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
37}
38
39static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev)
40{
41 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
42
43 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
44 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
45
46 return tmp;
47}
48
49static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
50{
51 if (enable)
52 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
53 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
54 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
55 else
56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
57}
58
59static u32 nbio_v4_3_get_memsize(struct amdgpu_device *adev)
60{
61 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
62}
63
64static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
65 bool use_doorbell, int doorbell_index,
66 int doorbell_size)
67{
68 if (instance == 0) {
69 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);
70
71 if (use_doorbell) {
72 doorbell_range = REG_SET_FIELD(doorbell_range,
73 S2A_DOORBELL_ENTRY_2_CTRL,
74 S2A_DOORBELL_PORT2_ENABLE,
75 0x1);
76 doorbell_range = REG_SET_FIELD(doorbell_range,
77 S2A_DOORBELL_ENTRY_2_CTRL,
78 S2A_DOORBELL_PORT2_AWID,
79 0xe);
80 doorbell_range = REG_SET_FIELD(doorbell_range,
81 S2A_DOORBELL_ENTRY_2_CTRL,
82 S2A_DOORBELL_PORT2_RANGE_OFFSET,
83 doorbell_index);
84 doorbell_range = REG_SET_FIELD(doorbell_range,
85 S2A_DOORBELL_ENTRY_2_CTRL,
86 S2A_DOORBELL_PORT2_RANGE_SIZE,
87 doorbell_size);
88 doorbell_range = REG_SET_FIELD(doorbell_range,
89 S2A_DOORBELL_ENTRY_2_CTRL,
90 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
91 0x3);
92 } else
93 doorbell_range = REG_SET_FIELD(doorbell_range,
94 S2A_DOORBELL_ENTRY_2_CTRL,
95 S2A_DOORBELL_PORT2_RANGE_SIZE,
96 0);
97
98 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
99 }
100}
101
102static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
103 int doorbell_index, int instance)
104{
105 u32 doorbell_range;
106
107 if (instance)
108 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL);
109 else
110 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL);
111
112 if (use_doorbell) {
113 doorbell_range = REG_SET_FIELD(doorbell_range,
114 S2A_DOORBELL_ENTRY_4_CTRL,
115 S2A_DOORBELL_PORT4_ENABLE,
116 0x1);
117 doorbell_range = REG_SET_FIELD(doorbell_range,
118 S2A_DOORBELL_ENTRY_4_CTRL,
119 S2A_DOORBELL_PORT4_AWID,
120 instance ? 0x7 : 0x4);
121 doorbell_range = REG_SET_FIELD(doorbell_range,
122 S2A_DOORBELL_ENTRY_4_CTRL,
123 S2A_DOORBELL_PORT4_RANGE_OFFSET,
124 doorbell_index);
125 doorbell_range = REG_SET_FIELD(doorbell_range,
126 S2A_DOORBELL_ENTRY_4_CTRL,
127 S2A_DOORBELL_PORT4_RANGE_SIZE,
128 8);
129 doorbell_range = REG_SET_FIELD(doorbell_range,
130 S2A_DOORBELL_ENTRY_4_CTRL,
131 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
132 instance ? 0x7 : 0x4);
133 } else
134 doorbell_range = REG_SET_FIELD(doorbell_range,
135 S2A_DOORBELL_ENTRY_4_CTRL,
136 S2A_DOORBELL_PORT4_RANGE_SIZE,
137 0);
138
139 if (instance)
140 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
141 else
142 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
143}
144
145static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev)
146{
147 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
148 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
149}
150
151static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev,
152 bool enable)
153{
154 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
155 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
156}
157
158static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
159 bool enable)
160{
161 u32 tmp = 0;
162
163 if (enable) {
164 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
165 DOORBELL_SELFRING_GPA_APER_EN, 1) |
166 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
167 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
168 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
169 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
170
171 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
172 lower_32_bits(adev->doorbell.base));
173 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
174 upper_32_bits(adev->doorbell.base));
175 }
176
177 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
178 tmp);
179}
180
181static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev,
182 bool use_doorbell, int doorbell_index)
183{
184 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);
185
186 if (use_doorbell) {
187 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
188 S2A_DOORBELL_ENTRY_1_CTRL,
189 S2A_DOORBELL_PORT1_ENABLE,
190 0x1);
191 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
192 S2A_DOORBELL_ENTRY_1_CTRL,
193 S2A_DOORBELL_PORT1_AWID,
194 0x0);
195 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
196 S2A_DOORBELL_ENTRY_1_CTRL,
197 S2A_DOORBELL_PORT1_RANGE_OFFSET,
198 doorbell_index);
199 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
200 S2A_DOORBELL_ENTRY_1_CTRL,
201 S2A_DOORBELL_PORT1_RANGE_SIZE,
202 2);
203 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
204 S2A_DOORBELL_ENTRY_1_CTRL,
205 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
206 0x0);
207 } else
208 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
209 S2A_DOORBELL_ENTRY_1_CTRL,
210 S2A_DOORBELL_PORT1_RANGE_SIZE,
211 0);
212
213 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
214}
215
216static void nbio_v4_3_ih_control(struct amdgpu_device *adev)
217{
218 u32 interrupt_cntl;
219
220 /* setup interrupt control */
221 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
222
223 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
224 /*
225 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
226 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
227 */
228 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
229 IH_DUMMY_RD_OVERRIDE, 0);
230
231 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
233 IH_REQ_NONSNOOP_EN, 0);
234
235 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
236}
237
238static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
239 bool enable)
240{
241 uint32_t def, data;
242
243 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
244 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
245 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
246 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
247 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
248 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
249 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
250 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
251 } else {
252 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
253 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
254 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
255 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
256 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
257 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
258 }
259
260 if (def != data)
261 WREG32_SOC15(NBIO, 0, regCPM_CONTROL, data);
262}
263
264static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
265 bool enable)
266{
267 uint32_t def, data;
268
269 /* TODO: need update in future */
270 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
271 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
272 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
273 } else {
274 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
275 }
276
277 if (def != data)
278 WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data);
279}
280
281static void nbio_v4_3_get_clockgating_state(struct amdgpu_device *adev,
282 u64 *flags)
283{
284 int data;
285
286 /* AMD_CG_SUPPORT_BIF_MGCG */
287 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);
288 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
289 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
290
291 /* AMD_CG_SUPPORT_BIF_LS */
292 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);
293 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
294 *flags |= AMD_CG_SUPPORT_BIF_LS;
295}
296
297static u32 nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
298{
299 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
300}
301
302static u32 nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
303{
304 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
305}
306
307static u32 nbio_v4_3_get_pcie_index_offset(struct amdgpu_device *adev)
308{
309 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
310}
311
312static u32 nbio_v4_3_get_pcie_data_offset(struct amdgpu_device *adev)
313{
314 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
315}
316
317const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = {
318 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
319 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
320 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
321 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
322 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
323 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
324 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
325 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
326 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
327 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
328 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
329 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
330};
331
332static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
333{
334 return;
335}
336
337static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
338{
339 u32 data, rom_offset;
340
341 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);
342 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
343
344 return rom_offset;
345}
346
347const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
348 .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
349 .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
350 .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset,
351 .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset,
352 .get_rev_id = nbio_v4_3_get_rev_id,
353 .mc_access_enable = nbio_v4_3_mc_access_enable,
354 .get_memsize = nbio_v4_3_get_memsize,
355 .sdma_doorbell_range = nbio_v4_3_sdma_doorbell_range,
356 .vcn_doorbell_range = nbio_v4_3_vcn_doorbell_range,
357 .gc_doorbell_init = nbio_v4_3_gc_doorbell_init,
358 .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture,
359 .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture,
360 .ih_doorbell_range = nbio_v4_3_ih_doorbell_range,
361 .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating,
362 .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep,
363 .get_clockgating_state = nbio_v4_3_get_clockgating_state,
364 .ih_control = nbio_v4_3_ih_control,
365 .init_registers = nbio_v4_3_init_registers,
366 .remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
367 .get_rom_offset = nbio_v4_3_get_rom_offset,
368};