tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * UFS PHY driver data for Samsung EXYNOS7 SoC
4 *
5 * Copyright (C) 2020 Samsung Electronics Co., Ltd.
6 */
7
8#include "phy-samsung-ufs.h"
9
10#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
11#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
12#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
13
14/* Calibration for phy initialization */
15static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = {
16 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
17 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
18 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
19 PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
20 PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
21 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
22 PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
23 PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
24 PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
25 PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
26 PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
27 PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
28 PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
29 PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
30 END_UFS_PHY_CFG
31};
32
33/* Calibration for HS mode series A/B */
34static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = {
35 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY),
36 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY),
37 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY),
38 /* Setting order: 1st(0x16, 2nd(0x15) */
39 PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY),
40 PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY),
41 PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY),
42 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY),
43 PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY),
44 PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY),
45 PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A),
46 PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B),
47 PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY),
48 PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY),
49 PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A),
50 PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B),
51 PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A),
52 PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B),
53 END_UFS_PHY_CFG
54};
55
56/* Calibration for HS mode series A/B atfer PMC */
57static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = {
58 PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY),
59 PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY),
60 END_UFS_PHY_CFG
61};
62
63static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = {
64 [CFG_PRE_INIT] = exynos7_pre_init_cfg,
65 [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg,
66 [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg,
67};
68
69const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
70 .cfg = exynos7_ufs_phy_cfgs,
71 .isol = {
72 .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL,
73 .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK,
74 .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN,
75 },
76 .has_symbol_clk = 1,
77};