tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_psp.h"
25#include "amdgpu_ucode.h"
26#include "soc15_common.h"
27#include "psp_v13_0.h"
28
29#include "mp/mp_13_0_2_offset.h"
30#include "mp/mp_13_0_2_sh_mask.h"
31
32MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
33MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
34MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
35MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
36MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
37MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
38MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin");
39MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
40MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
41MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin");
42MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44
45/* For large FW files the time to complete can be very long */
46#define USBC_PD_POLLING_LIMIT_S 240
47
48/* Read USB-PD from LFB */
49#define GFX_CMD_USB_PD_USE_LFB 0x480
50
51static int psp_v13_0_init_microcode(struct psp_context *psp)
52{
53 struct amdgpu_device *adev = psp->adev;
54 const char *chip_name;
55 int err = 0;
56
57 switch (adev->ip_versions[MP0_HWIP][0]) {
58 case IP_VERSION(13, 0, 2):
59 chip_name = "aldebaran";
60 break;
61 case IP_VERSION(13, 0, 1):
62 case IP_VERSION(13, 0, 3):
63 chip_name = "yellow_carp";
64 break;
65 case IP_VERSION(13, 0, 5):
66 chip_name = "psp_13_0_5";
67 break;
68 case IP_VERSION(13, 0, 8):
69 chip_name = "psp_13_0_8";
70 break;
71 default:
72 BUG();
73 }
74 switch (adev->ip_versions[MP0_HWIP][0]) {
75 case IP_VERSION(13, 0, 2):
76 err = psp_init_sos_microcode(psp, chip_name);
77 if (err)
78 return err;
79 err = psp_init_ta_microcode(&adev->psp, chip_name);
80 if (err)
81 return err;
82 break;
83 case IP_VERSION(13, 0, 1):
84 case IP_VERSION(13, 0, 3):
85 case IP_VERSION(13, 0, 5):
86 case IP_VERSION(13, 0, 8):
87 err = psp_init_asd_microcode(psp, chip_name);
88 if (err)
89 return err;
90 err = psp_init_toc_microcode(psp, chip_name);
91 if (err)
92 return err;
93 err = psp_init_ta_microcode(psp, chip_name);
94 if (err)
95 return err;
96 break;
97 default:
98 BUG();
99 }
100
101 return 0;
102}
103
104static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
105{
106 struct amdgpu_device *adev = psp->adev;
107 uint32_t sol_reg;
108
109 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
110
111 return sol_reg != 0x0;
112}
113
114static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
115{
116 struct amdgpu_device *adev = psp->adev;
117
118 int ret;
119 int retry_loop;
120
121 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
122 /* Wait for bootloader to signify that is
123 ready having bit 31 of C2PMSG_35 set to 1 */
124 ret = psp_wait_for(psp,
125 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
126 0x80000000,
127 0x80000000,
128 false);
129
130 if (ret == 0)
131 return 0;
132 }
133
134 return ret;
135}
136
137static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
138 struct psp_bin_desc *bin_desc,
139 enum psp_bootloader_cmd bl_cmd)
140{
141 int ret;
142 uint32_t psp_gfxdrv_command_reg = 0;
143 struct amdgpu_device *adev = psp->adev;
144
145 /* Check tOS sign of life register to confirm sys driver and sOS
146 * are already been loaded.
147 */
148 if (psp_v13_0_is_sos_alive(psp))
149 return 0;
150
151 ret = psp_v13_0_wait_for_bootloader(psp);
152 if (ret)
153 return ret;
154
155 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
156
157 /* Copy PSP KDB binary to memory */
158 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
159
160 /* Provide the PSP KDB to bootloader */
161 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
162 (uint32_t)(psp->fw_pri_mc_addr >> 20));
163 psp_gfxdrv_command_reg = bl_cmd;
164 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
165 psp_gfxdrv_command_reg);
166
167 ret = psp_v13_0_wait_for_bootloader(psp);
168
169 return ret;
170}
171
172static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
173{
174 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
175}
176
177static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
178{
179 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
180}
181
182static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
183{
184 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
185}
186
187static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
188{
189 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
190}
191
192static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
193{
194 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
195}
196
197static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
198{
199 int ret;
200 unsigned int psp_gfxdrv_command_reg = 0;
201 struct amdgpu_device *adev = psp->adev;
202
203 /* Check sOS sign of life register to confirm sys driver and sOS
204 * are already been loaded.
205 */
206 if (psp_v13_0_is_sos_alive(psp))
207 return 0;
208
209 ret = psp_v13_0_wait_for_bootloader(psp);
210 if (ret)
211 return ret;
212
213 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
214
215 /* Copy Secure OS binary to PSP memory */
216 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
217
218 /* Provide the PSP secure OS to bootloader */
219 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
220 (uint32_t)(psp->fw_pri_mc_addr >> 20));
221 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
222 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
223 psp_gfxdrv_command_reg);
224
225 /* there might be handshake issue with hardware which needs delay */
226 mdelay(20);
227 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
228 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
229 0, true);
230
231 return ret;
232}
233
234static int psp_v13_0_ring_init(struct psp_context *psp,
235 enum psp_ring_type ring_type)
236{
237 int ret = 0;
238 struct psp_ring *ring;
239 struct amdgpu_device *adev = psp->adev;
240
241 ring = &psp->km_ring;
242
243 ring->ring_type = ring_type;
244
245 /* allocate 4k Page of Local Frame Buffer memory for ring */
246 ring->ring_size = 0x1000;
247 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
248 AMDGPU_GEM_DOMAIN_VRAM,
249 &adev->firmware.rbuf,
250 &ring->ring_mem_mc_addr,
251 (void **)&ring->ring_mem);
252 if (ret) {
253 ring->ring_size = 0;
254 return ret;
255 }
256
257 return 0;
258}
259
260static int psp_v13_0_ring_stop(struct psp_context *psp,
261 enum psp_ring_type ring_type)
262{
263 int ret = 0;
264 struct amdgpu_device *adev = psp->adev;
265
266 if (amdgpu_sriov_vf(adev)) {
267 /* Write the ring destroy command*/
268 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
269 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
270 /* there might be handshake issue with hardware which needs delay */
271 mdelay(20);
272 /* Wait for response flag (bit 31) */
273 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
274 0x80000000, 0x80000000, false);
275 } else {
276 /* Write the ring destroy command*/
277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
278 GFX_CTRL_CMD_ID_DESTROY_RINGS);
279 /* there might be handshake issue with hardware which needs delay */
280 mdelay(20);
281 /* Wait for response flag (bit 31) */
282 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
283 0x80000000, 0x80000000, false);
284 }
285
286 return ret;
287}
288
289static int psp_v13_0_ring_create(struct psp_context *psp,
290 enum psp_ring_type ring_type)
291{
292 int ret = 0;
293 unsigned int psp_ring_reg = 0;
294 struct psp_ring *ring = &psp->km_ring;
295 struct amdgpu_device *adev = psp->adev;
296
297 if (amdgpu_sriov_vf(adev)) {
298 ret = psp_v13_0_ring_stop(psp, ring_type);
299 if (ret) {
300 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
301 return ret;
302 }
303
304 /* Write low address of the ring to C2PMSG_102 */
305 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
306 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
307 /* Write high address of the ring to C2PMSG_103 */
308 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
309 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
310
311 /* Write the ring initialization command to C2PMSG_101 */
312 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
313 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
314
315 /* there might be handshake issue with hardware which needs delay */
316 mdelay(20);
317
318 /* Wait for response flag (bit 31) in C2PMSG_101 */
319 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
320 0x80000000, 0x8000FFFF, false);
321
322 } else {
323 /* Wait for sOS ready for ring creation */
324 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
325 0x80000000, 0x80000000, false);
326 if (ret) {
327 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
328 return ret;
329 }
330
331 /* Write low address of the ring to C2PMSG_69 */
332 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
333 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
334 /* Write high address of the ring to C2PMSG_70 */
335 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
336 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
337 /* Write size of ring to C2PMSG_71 */
338 psp_ring_reg = ring->ring_size;
339 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
340 /* Write the ring initialization command to C2PMSG_64 */
341 psp_ring_reg = ring_type;
342 psp_ring_reg = psp_ring_reg << 16;
343 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
344
345 /* there might be handshake issue with hardware which needs delay */
346 mdelay(20);
347
348 /* Wait for response flag (bit 31) in C2PMSG_64 */
349 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
350 0x80000000, 0x8000FFFF, false);
351 }
352
353 return ret;
354}
355
356static int psp_v13_0_ring_destroy(struct psp_context *psp,
357 enum psp_ring_type ring_type)
358{
359 int ret = 0;
360 struct psp_ring *ring = &psp->km_ring;
361 struct amdgpu_device *adev = psp->adev;
362
363 ret = psp_v13_0_ring_stop(psp, ring_type);
364 if (ret)
365 DRM_ERROR("Fail to stop psp ring\n");
366
367 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
368 &ring->ring_mem_mc_addr,
369 (void **)&ring->ring_mem);
370
371 return ret;
372}
373
374static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
375{
376 uint32_t data;
377 struct amdgpu_device *adev = psp->adev;
378
379 if (amdgpu_sriov_vf(adev))
380 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
381 else
382 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
383
384 return data;
385}
386
387static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
388{
389 struct amdgpu_device *adev = psp->adev;
390
391 if (amdgpu_sriov_vf(adev)) {
392 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
393 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
394 GFX_CTRL_CMD_ID_CONSUME_CMD);
395 } else
396 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
397}
398
399static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
400{
401 struct amdgpu_device *adev = psp->adev;
402 uint32_t reg_status;
403 int ret, i = 0;
404
405 /*
406 * LFB address which is aligned to 1MB address and has to be
407 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
408 * register
409 */
410 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
411
412 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
413 0x80000000, 0x80000000, false);
414 if (ret)
415 return ret;
416
417 /* Fireup interrupt so PSP can pick up the address */
418 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
419
420 /* FW load takes very long time */
421 do {
422 msleep(1000);
423 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
424
425 if (reg_status & 0x80000000)
426 goto done;
427
428 } while (++i < USBC_PD_POLLING_LIMIT_S);
429
430 return -ETIME;
431done:
432
433 if ((reg_status & 0xFFFF) != 0) {
434 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
435 reg_status & 0xFFFF);
436 return -EIO;
437 }
438
439 return 0;
440}
441
442static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
443{
444 struct amdgpu_device *adev = psp->adev;
445 int ret;
446
447 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
448
449 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
450 0x80000000, 0x80000000, false);
451 if (!ret)
452 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
453
454 return ret;
455}
456
457static const struct psp_funcs psp_v13_0_funcs = {
458 .init_microcode = psp_v13_0_init_microcode,
459 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
460 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
461 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
462 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
463 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
464 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
465 .ring_init = psp_v13_0_ring_init,
466 .ring_create = psp_v13_0_ring_create,
467 .ring_stop = psp_v13_0_ring_stop,
468 .ring_destroy = psp_v13_0_ring_destroy,
469 .ring_get_wptr = psp_v13_0_ring_get_wptr,
470 .ring_set_wptr = psp_v13_0_ring_set_wptr,
471 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
472 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw
473};
474
475void psp_v13_0_set_psp_funcs(struct psp_context *psp)
476{
477 psp->funcs = &psp_v13_0_funcs;
478}