tjh.dev
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1/*
2 * TI Clock driver internal definitions
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc
5 * Tero Kristo (t-kristo@ti.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__
18
19struct clk_omap_divider {
20 struct clk_hw hw;
21 struct clk_omap_reg reg;
22 u8 shift;
23 u8 flags;
24 s8 latch;
25 u16 min;
26 u16 max;
27 u16 mask;
28 const struct clk_div_table *table;
29 u32 context;
30};
31
32#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
33
34struct clk_omap_mux {
35 struct clk_hw hw;
36 struct clk_omap_reg reg;
37 u32 *table;
38 u32 mask;
39 u8 shift;
40 s8 latch;
41 u8 flags;
42 u8 saved_parent;
43};
44
45#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
46
47enum {
48 TI_CLK_FIXED,
49 TI_CLK_MUX,
50 TI_CLK_DIVIDER,
51 TI_CLK_COMPOSITE,
52 TI_CLK_FIXED_FACTOR,
53 TI_CLK_GATE,
54 TI_CLK_DPLL,
55};
56
57/* Global flags */
58#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
59#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
60#define CLKF_SET_RATE_PARENT (1 << 2)
61#define CLKF_OMAP3 (1 << 3)
62#define CLKF_AM35XX (1 << 4)
63
64/* Gate flags */
65#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
66#define CLKF_INTERFACE (1 << 6)
67#define CLKF_SSI (1 << 7)
68#define CLKF_DSS (1 << 8)
69#define CLKF_HSOTGUSB (1 << 9)
70#define CLKF_WAIT (1 << 10)
71#define CLKF_NO_WAIT (1 << 11)
72#define CLKF_HSDIV (1 << 12)
73#define CLKF_CLKDM (1 << 13)
74
75/* DPLL flags */
76#define CLKF_LOW_POWER_STOP (1 << 5)
77#define CLKF_LOCK (1 << 6)
78#define CLKF_LOW_POWER_BYPASS (1 << 7)
79#define CLKF_PER (1 << 8)
80#define CLKF_CORE (1 << 9)
81#define CLKF_J_TYPE (1 << 10)
82
83/* CLKCTRL flags */
84#define CLKF_SW_SUP BIT(5)
85#define CLKF_HW_SUP BIT(6)
86#define CLKF_NO_IDLEST BIT(7)
87
88#define CLKF_SOC_MASK GENMASK(11, 8)
89
90#define CLKF_SOC_NONSEC BIT(8)
91#define CLKF_SOC_DRA72 BIT(9)
92#define CLKF_SOC_DRA74 BIT(10)
93#define CLKF_SOC_DRA76 BIT(11)
94
95#define CLK(dev, con, ck) \
96 { \
97 .lk = { \
98 .dev_id = dev, \
99 .con_id = con, \
100 }, \
101 .clk = ck, \
102 }
103
104struct ti_clk {
105 const char *name;
106 const char *clkdm_name;
107 int type;
108 void *data;
109 struct ti_clk *patch;
110 struct clk *clk;
111};
112
113struct ti_clk_mux {
114 u8 bit_shift;
115 int num_parents;
116 u16 reg;
117 u8 module;
118 const char * const *parents;
119 u16 flags;
120};
121
122struct ti_clk_divider {
123 const char *parent;
124 u8 bit_shift;
125 u16 max_div;
126 u16 reg;
127 u8 module;
128 int *dividers;
129 int num_dividers;
130 u16 flags;
131};
132
133struct ti_clk_gate {
134 const char *parent;
135 u8 bit_shift;
136 u16 reg;
137 u8 module;
138 u16 flags;
139};
140
141/* Composite clock component types */
142enum {
143 CLK_COMPONENT_TYPE_GATE = 0,
144 CLK_COMPONENT_TYPE_DIVIDER,
145 CLK_COMPONENT_TYPE_MUX,
146 CLK_COMPONENT_TYPE_MAX,
147};
148
149/**
150 * struct ti_dt_clk - OMAP DT clock alias declarations
151 * @lk: clock lookup definition
152 * @node_name: clock DT node to map to
153 */
154struct ti_dt_clk {
155 struct clk_lookup lk;
156 char *node_name;
157};
158
159#define DT_CLK(dev, con, name) \
160 { \
161 .lk = { \
162 .dev_id = dev, \
163 .con_id = con, \
164 }, \
165 .node_name = name, \
166 }
167
168/* CLKCTRL type definitions */
169struct omap_clkctrl_div_data {
170 const int *dividers;
171 int max_div;
172 u32 flags;
173};
174
175struct omap_clkctrl_bit_data {
176 u8 bit;
177 u8 type;
178 const char * const *parents;
179 const void *data;
180};
181
182struct omap_clkctrl_reg_data {
183 u16 offset;
184 const struct omap_clkctrl_bit_data *bit_data;
185 u16 flags;
186 const char *parent;
187 const char *clkdm_name;
188};
189
190struct omap_clkctrl_data {
191 u32 addr;
192 const struct omap_clkctrl_reg_data *regs;
193};
194
195extern const struct omap_clkctrl_data omap4_clkctrl_data[];
196extern const struct omap_clkctrl_data omap5_clkctrl_data[];
197extern const struct omap_clkctrl_data dra7_clkctrl_data[];
198extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
199extern struct ti_dt_clk dra7xx_compat_clks[];
200extern const struct omap_clkctrl_data am3_clkctrl_data[];
201extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
202extern struct ti_dt_clk am33xx_compat_clks[];
203extern const struct omap_clkctrl_data am4_clkctrl_data[];
204extern const struct omap_clkctrl_data am438x_clkctrl_data[];
205extern const struct omap_clkctrl_data dm814_clkctrl_data[];
206extern const struct omap_clkctrl_data dm816_clkctrl_data[];
207
208typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
209
210struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
211 const char *con);
212struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
213 const char *con);
214const char *ti_dt_clk_name(struct device_node *np);
215int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
216void ti_clk_add_aliases(void);
217
218void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
219
220struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
221
222int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
223 u8 flags, struct clk_omap_divider *div);
224
225int ti_clk_get_reg_addr(struct device_node *node, int index,
226 struct clk_omap_reg *reg);
227void ti_dt_clocks_register(struct ti_dt_clk *oclks);
228int ti_clk_retry_init(struct device_node *node, void *user,
229 ti_of_clk_init_cb_t func);
230int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
231
232int of_ti_clk_autoidle_setup(struct device_node *node);
233void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
234
235extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
236extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
237extern const struct clk_hw_omap_ops clkhwops_wait;
238extern const struct clk_hw_omap_ops clkhwops_iclk;
239extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
240extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
241extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
242extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
243extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
244extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
245extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
246extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
247
248extern const struct clk_ops ti_clk_divider_ops;
249extern const struct clk_ops ti_clk_mux_ops;
250extern const struct clk_ops omap_gate_clk_ops;
251
252extern struct ti_clk_features ti_clk_features;
253
254int omap2_init_clk_clkdm(struct clk_hw *hw);
255int omap2_clkops_enable_clkdm(struct clk_hw *hw);
256void omap2_clkops_disable_clkdm(struct clk_hw *hw);
257
258int omap2_dflt_clk_enable(struct clk_hw *hw);
259void omap2_dflt_clk_disable(struct clk_hw *hw);
260int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
261void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
262 struct clk_omap_reg *other_reg,
263 u8 *other_bit);
264void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
265 struct clk_omap_reg *idlest_reg,
266 u8 *idlest_bit, u8 *idlest_val);
267
268void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
269void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
270
271u8 omap2_init_dpll_parent(struct clk_hw *hw);
272int omap3_noncore_dpll_enable(struct clk_hw *hw);
273void omap3_noncore_dpll_disable(struct clk_hw *hw);
274int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
275int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
276 unsigned long parent_rate);
277int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
278 unsigned long rate,
279 unsigned long parent_rate,
280 u8 index);
281int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
282 struct clk_rate_request *req);
283long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
284 unsigned long *parent_rate);
285unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
286 unsigned long parent_rate);
287
288/*
289 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
290 * that are sourced by DPLL5, and both of these require this clock
291 * to be at 120 MHz for proper operation.
292 */
293#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
294
295unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
296int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
297 unsigned long parent_rate);
298int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
299 unsigned long parent_rate, u8 index);
300int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
301 unsigned long parent_rate);
302void omap3_clk_lock_dpll5(void);
303
304unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
305 unsigned long parent_rate);
306long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
307 unsigned long target_rate,
308 unsigned long *parent_rate);
309int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
310 struct clk_rate_request *req);
311int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
312
313extern struct ti_clk_ll_ops *ti_clk_ll_ops;
314
315#endif