tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Huawei Ltd.
4 * Author: Jiang Liu <liuj97@gmail.com>
5 *
6 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7 */
8#ifndef __ASM_INSN_H
9#define __ASM_INSN_H
10#include <linux/build_bug.h>
11#include <linux/types.h>
12
13#include <asm/insn-def.h>
14
15#ifndef __ASSEMBLY__
16/*
17 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
18 * Section C3.1 "A64 instruction index by encoding":
19 * AArch64 main encoding table
20 * Bit position
21 * 28 27 26 25 Encoding Group
22 * 0 0 - - Unallocated
23 * 1 0 0 - Data processing, immediate
24 * 1 0 1 - Branch, exception generation and system instructions
25 * - 1 - 0 Loads and stores
26 * - 1 0 1 Data processing - register
27 * 0 1 1 1 Data processing - SIMD and floating point
28 * 1 1 1 1 Data processing - SIMD and floating point
29 * "-" means "don't care"
30 */
31enum aarch64_insn_encoding_class {
32 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
33 AARCH64_INSN_CLS_SVE, /* SVE instructions */
34 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
35 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
36 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
37 AARCH64_INSN_CLS_LDST, /* Loads and stores */
38 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
39 * system instructions */
40};
41
42enum aarch64_insn_hint_cr_op {
43 AARCH64_INSN_HINT_NOP = 0x0 << 5,
44 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
45 AARCH64_INSN_HINT_WFE = 0x2 << 5,
46 AARCH64_INSN_HINT_WFI = 0x3 << 5,
47 AARCH64_INSN_HINT_SEV = 0x4 << 5,
48 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
49
50 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
51 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
52 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
53 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
54 AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
55 AARCH64_INSN_HINT_PACIAZ = 0x18 << 5,
56 AARCH64_INSN_HINT_PACIASP = 0x19 << 5,
57 AARCH64_INSN_HINT_PACIBZ = 0x1A << 5,
58 AARCH64_INSN_HINT_PACIBSP = 0x1B << 5,
59 AARCH64_INSN_HINT_AUTIAZ = 0x1C << 5,
60 AARCH64_INSN_HINT_AUTIASP = 0x1D << 5,
61 AARCH64_INSN_HINT_AUTIBZ = 0x1E << 5,
62 AARCH64_INSN_HINT_AUTIBSP = 0x1F << 5,
63
64 AARCH64_INSN_HINT_ESB = 0x10 << 5,
65 AARCH64_INSN_HINT_PSB = 0x11 << 5,
66 AARCH64_INSN_HINT_TSB = 0x12 << 5,
67 AARCH64_INSN_HINT_CSDB = 0x14 << 5,
68 AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
69
70 AARCH64_INSN_HINT_BTI = 0x20 << 5,
71 AARCH64_INSN_HINT_BTIC = 0x22 << 5,
72 AARCH64_INSN_HINT_BTIJ = 0x24 << 5,
73 AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
74};
75
76enum aarch64_insn_imm_type {
77 AARCH64_INSN_IMM_ADR,
78 AARCH64_INSN_IMM_26,
79 AARCH64_INSN_IMM_19,
80 AARCH64_INSN_IMM_16,
81 AARCH64_INSN_IMM_14,
82 AARCH64_INSN_IMM_12,
83 AARCH64_INSN_IMM_9,
84 AARCH64_INSN_IMM_7,
85 AARCH64_INSN_IMM_6,
86 AARCH64_INSN_IMM_S,
87 AARCH64_INSN_IMM_R,
88 AARCH64_INSN_IMM_N,
89 AARCH64_INSN_IMM_MAX
90};
91
92enum aarch64_insn_register_type {
93 AARCH64_INSN_REGTYPE_RT,
94 AARCH64_INSN_REGTYPE_RN,
95 AARCH64_INSN_REGTYPE_RT2,
96 AARCH64_INSN_REGTYPE_RM,
97 AARCH64_INSN_REGTYPE_RD,
98 AARCH64_INSN_REGTYPE_RA,
99 AARCH64_INSN_REGTYPE_RS,
100};
101
102enum aarch64_insn_register {
103 AARCH64_INSN_REG_0 = 0,
104 AARCH64_INSN_REG_1 = 1,
105 AARCH64_INSN_REG_2 = 2,
106 AARCH64_INSN_REG_3 = 3,
107 AARCH64_INSN_REG_4 = 4,
108 AARCH64_INSN_REG_5 = 5,
109 AARCH64_INSN_REG_6 = 6,
110 AARCH64_INSN_REG_7 = 7,
111 AARCH64_INSN_REG_8 = 8,
112 AARCH64_INSN_REG_9 = 9,
113 AARCH64_INSN_REG_10 = 10,
114 AARCH64_INSN_REG_11 = 11,
115 AARCH64_INSN_REG_12 = 12,
116 AARCH64_INSN_REG_13 = 13,
117 AARCH64_INSN_REG_14 = 14,
118 AARCH64_INSN_REG_15 = 15,
119 AARCH64_INSN_REG_16 = 16,
120 AARCH64_INSN_REG_17 = 17,
121 AARCH64_INSN_REG_18 = 18,
122 AARCH64_INSN_REG_19 = 19,
123 AARCH64_INSN_REG_20 = 20,
124 AARCH64_INSN_REG_21 = 21,
125 AARCH64_INSN_REG_22 = 22,
126 AARCH64_INSN_REG_23 = 23,
127 AARCH64_INSN_REG_24 = 24,
128 AARCH64_INSN_REG_25 = 25,
129 AARCH64_INSN_REG_26 = 26,
130 AARCH64_INSN_REG_27 = 27,
131 AARCH64_INSN_REG_28 = 28,
132 AARCH64_INSN_REG_29 = 29,
133 AARCH64_INSN_REG_FP = 29, /* Frame pointer */
134 AARCH64_INSN_REG_30 = 30,
135 AARCH64_INSN_REG_LR = 30, /* Link register */
136 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
137 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
138};
139
140enum aarch64_insn_special_register {
141 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
142 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
143 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
144 AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
145 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
146 AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
147 AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
148 AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
149 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
150 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
151 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
152 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
153 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
154 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
155 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
156 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
157 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
158 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
159 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
160 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
161};
162
163enum aarch64_insn_variant {
164 AARCH64_INSN_VARIANT_32BIT,
165 AARCH64_INSN_VARIANT_64BIT
166};
167
168enum aarch64_insn_condition {
169 AARCH64_INSN_COND_EQ = 0x0, /* == */
170 AARCH64_INSN_COND_NE = 0x1, /* != */
171 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
172 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
173 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
174 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
175 AARCH64_INSN_COND_VS = 0x6, /* overflow */
176 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
177 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
178 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
179 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
180 AARCH64_INSN_COND_LT = 0xb, /* signed < */
181 AARCH64_INSN_COND_GT = 0xc, /* signed > */
182 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
183 AARCH64_INSN_COND_AL = 0xe, /* always */
184};
185
186enum aarch64_insn_branch_type {
187 AARCH64_INSN_BRANCH_NOLINK,
188 AARCH64_INSN_BRANCH_LINK,
189 AARCH64_INSN_BRANCH_RETURN,
190 AARCH64_INSN_BRANCH_COMP_ZERO,
191 AARCH64_INSN_BRANCH_COMP_NONZERO,
192};
193
194enum aarch64_insn_size_type {
195 AARCH64_INSN_SIZE_8,
196 AARCH64_INSN_SIZE_16,
197 AARCH64_INSN_SIZE_32,
198 AARCH64_INSN_SIZE_64,
199};
200
201enum aarch64_insn_ldst_type {
202 AARCH64_INSN_LDST_LOAD_REG_OFFSET,
203 AARCH64_INSN_LDST_STORE_REG_OFFSET,
204 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
205 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
206 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
207 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
208 AARCH64_INSN_LDST_LOAD_EX,
209 AARCH64_INSN_LDST_LOAD_ACQ_EX,
210 AARCH64_INSN_LDST_STORE_EX,
211 AARCH64_INSN_LDST_STORE_REL_EX,
212};
213
214enum aarch64_insn_adsb_type {
215 AARCH64_INSN_ADSB_ADD,
216 AARCH64_INSN_ADSB_SUB,
217 AARCH64_INSN_ADSB_ADD_SETFLAGS,
218 AARCH64_INSN_ADSB_SUB_SETFLAGS
219};
220
221enum aarch64_insn_movewide_type {
222 AARCH64_INSN_MOVEWIDE_ZERO,
223 AARCH64_INSN_MOVEWIDE_KEEP,
224 AARCH64_INSN_MOVEWIDE_INVERSE
225};
226
227enum aarch64_insn_bitfield_type {
228 AARCH64_INSN_BITFIELD_MOVE,
229 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
230 AARCH64_INSN_BITFIELD_MOVE_SIGNED
231};
232
233enum aarch64_insn_data1_type {
234 AARCH64_INSN_DATA1_REVERSE_16,
235 AARCH64_INSN_DATA1_REVERSE_32,
236 AARCH64_INSN_DATA1_REVERSE_64,
237};
238
239enum aarch64_insn_data2_type {
240 AARCH64_INSN_DATA2_UDIV,
241 AARCH64_INSN_DATA2_SDIV,
242 AARCH64_INSN_DATA2_LSLV,
243 AARCH64_INSN_DATA2_LSRV,
244 AARCH64_INSN_DATA2_ASRV,
245 AARCH64_INSN_DATA2_RORV,
246};
247
248enum aarch64_insn_data3_type {
249 AARCH64_INSN_DATA3_MADD,
250 AARCH64_INSN_DATA3_MSUB,
251};
252
253enum aarch64_insn_logic_type {
254 AARCH64_INSN_LOGIC_AND,
255 AARCH64_INSN_LOGIC_BIC,
256 AARCH64_INSN_LOGIC_ORR,
257 AARCH64_INSN_LOGIC_ORN,
258 AARCH64_INSN_LOGIC_EOR,
259 AARCH64_INSN_LOGIC_EON,
260 AARCH64_INSN_LOGIC_AND_SETFLAGS,
261 AARCH64_INSN_LOGIC_BIC_SETFLAGS
262};
263
264enum aarch64_insn_prfm_type {
265 AARCH64_INSN_PRFM_TYPE_PLD,
266 AARCH64_INSN_PRFM_TYPE_PLI,
267 AARCH64_INSN_PRFM_TYPE_PST,
268};
269
270enum aarch64_insn_prfm_target {
271 AARCH64_INSN_PRFM_TARGET_L1,
272 AARCH64_INSN_PRFM_TARGET_L2,
273 AARCH64_INSN_PRFM_TARGET_L3,
274};
275
276enum aarch64_insn_prfm_policy {
277 AARCH64_INSN_PRFM_POLICY_KEEP,
278 AARCH64_INSN_PRFM_POLICY_STRM,
279};
280
281enum aarch64_insn_adr_type {
282 AARCH64_INSN_ADR_TYPE_ADRP,
283 AARCH64_INSN_ADR_TYPE_ADR,
284};
285
286enum aarch64_insn_mem_atomic_op {
287 AARCH64_INSN_MEM_ATOMIC_ADD,
288 AARCH64_INSN_MEM_ATOMIC_CLR,
289 AARCH64_INSN_MEM_ATOMIC_EOR,
290 AARCH64_INSN_MEM_ATOMIC_SET,
291 AARCH64_INSN_MEM_ATOMIC_SWP,
292};
293
294enum aarch64_insn_mem_order_type {
295 AARCH64_INSN_MEM_ORDER_NONE,
296 AARCH64_INSN_MEM_ORDER_ACQ,
297 AARCH64_INSN_MEM_ORDER_REL,
298 AARCH64_INSN_MEM_ORDER_ACQREL,
299};
300
301enum aarch64_insn_mb_type {
302 AARCH64_INSN_MB_SY,
303 AARCH64_INSN_MB_ST,
304 AARCH64_INSN_MB_LD,
305 AARCH64_INSN_MB_ISH,
306 AARCH64_INSN_MB_ISHST,
307 AARCH64_INSN_MB_ISHLD,
308 AARCH64_INSN_MB_NSH,
309 AARCH64_INSN_MB_NSHST,
310 AARCH64_INSN_MB_NSHLD,
311 AARCH64_INSN_MB_OSH,
312 AARCH64_INSN_MB_OSHST,
313 AARCH64_INSN_MB_OSHLD,
314};
315
316#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
317static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
318{ \
319 BUILD_BUG_ON(~(mask) & (val)); \
320 return (code & (mask)) == (val); \
321} \
322static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
323{ \
324 return (val); \
325}
326
327__AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
328__AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
329__AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
330__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
331__AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
332__AARCH64_INSN_FUNCS(load_imm, 0x3FC00000, 0x39400000)
333__AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
334__AARCH64_INSN_FUNCS(load_pre, 0x3FE00C00, 0x38400C00)
335__AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400)
336__AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
337__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
338__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
339__AARCH64_INSN_FUNCS(ldclr, 0x3F20FC00, 0x38201000)
340__AARCH64_INSN_FUNCS(ldeor, 0x3F20FC00, 0x38202000)
341__AARCH64_INSN_FUNCS(ldset, 0x3F20FC00, 0x38203000)
342__AARCH64_INSN_FUNCS(swp, 0x3F20FC00, 0x38208000)
343__AARCH64_INSN_FUNCS(cas, 0x3FA07C00, 0x08A07C00)
344__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
345__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
346__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
347__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
348__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
349__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
350__AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000)
351__AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)
352__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
353__AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
354__AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
355__AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
356__AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
357__AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
358__AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
359__AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
360__AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
361__AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
362__AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
363__AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
364__AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
365__AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
366__AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
367__AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
368__AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
369__AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
370__AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
371__AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
372__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
373__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
374__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
375__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
376__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
377__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
378__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
379__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
380__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
381__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
382__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
383__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
384__AARCH64_INSN_FUNCS(mov_reg, 0x7FE0FFE0, 0x2A0003E0)
385__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
386__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
387__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
388__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
389__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
390__AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
391__AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
392__AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
393__AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
394__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
395__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
396__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
397__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
398__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
399__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
400__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
401__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
402__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
403__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
404__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
405__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
406__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
407__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
408__AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
409__AARCH64_INSN_FUNCS(br_auth, 0xFEFFF800, 0xD61F0800)
410__AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
411__AARCH64_INSN_FUNCS(blr_auth, 0xFEFFF800, 0xD63F0800)
412__AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
413__AARCH64_INSN_FUNCS(ret_auth, 0xFFFFFBFF, 0xD65F0BFF)
414__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
415__AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
416__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
417__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
418__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
419__AARCH64_INSN_FUNCS(dmb, 0xFFFFF0FF, 0xD50330BF)
420__AARCH64_INSN_FUNCS(dsb_base, 0xFFFFF0FF, 0xD503309F)
421__AARCH64_INSN_FUNCS(dsb_nxs, 0xFFFFF3FF, 0xD503323F)
422__AARCH64_INSN_FUNCS(isb, 0xFFFFF0FF, 0xD50330DF)
423__AARCH64_INSN_FUNCS(sb, 0xFFFFFFFF, 0xD50330FF)
424__AARCH64_INSN_FUNCS(clrex, 0xFFFFF0FF, 0xD503305F)
425__AARCH64_INSN_FUNCS(ssbb, 0xFFFFFFFF, 0xD503309F)
426__AARCH64_INSN_FUNCS(pssbb, 0xFFFFFFFF, 0xD503349F)
427
428#undef __AARCH64_INSN_FUNCS
429
430bool aarch64_insn_is_steppable_hint(u32 insn);
431bool aarch64_insn_is_branch_imm(u32 insn);
432
433static inline bool aarch64_insn_is_adr_adrp(u32 insn)
434{
435 return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
436}
437
438static inline bool aarch64_insn_is_dsb(u32 insn)
439{
440 return aarch64_insn_is_dsb_base(insn) || aarch64_insn_is_dsb_nxs(insn);
441}
442
443static inline bool aarch64_insn_is_barrier(u32 insn)
444{
445 return aarch64_insn_is_dmb(insn) || aarch64_insn_is_dsb(insn) ||
446 aarch64_insn_is_isb(insn) || aarch64_insn_is_sb(insn) ||
447 aarch64_insn_is_clrex(insn) || aarch64_insn_is_ssbb(insn) ||
448 aarch64_insn_is_pssbb(insn);
449}
450
451static inline bool aarch64_insn_is_store_single(u32 insn)
452{
453 return aarch64_insn_is_store_imm(insn) ||
454 aarch64_insn_is_store_pre(insn) ||
455 aarch64_insn_is_store_post(insn);
456}
457
458static inline bool aarch64_insn_is_store_pair(u32 insn)
459{
460 return aarch64_insn_is_stp(insn) ||
461 aarch64_insn_is_stp_pre(insn) ||
462 aarch64_insn_is_stp_post(insn);
463}
464
465static inline bool aarch64_insn_is_load_single(u32 insn)
466{
467 return aarch64_insn_is_load_imm(insn) ||
468 aarch64_insn_is_load_pre(insn) ||
469 aarch64_insn_is_load_post(insn);
470}
471
472static inline bool aarch64_insn_is_load_pair(u32 insn)
473{
474 return aarch64_insn_is_ldp(insn) ||
475 aarch64_insn_is_ldp_pre(insn) ||
476 aarch64_insn_is_ldp_post(insn);
477}
478
479enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
480bool aarch64_insn_uses_literal(u32 insn);
481bool aarch64_insn_is_branch(u32 insn);
482u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
483u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
484 u32 insn, u64 imm);
485u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
486 u32 insn);
487u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
488 enum aarch64_insn_branch_type type);
489u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
490 enum aarch64_insn_register reg,
491 enum aarch64_insn_variant variant,
492 enum aarch64_insn_branch_type type);
493u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
494 enum aarch64_insn_condition cond);
495u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op);
496u32 aarch64_insn_gen_nop(void);
497u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
498 enum aarch64_insn_branch_type type);
499u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
500 enum aarch64_insn_register base,
501 enum aarch64_insn_register offset,
502 enum aarch64_insn_size_type size,
503 enum aarch64_insn_ldst_type type);
504u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
505 enum aarch64_insn_register reg2,
506 enum aarch64_insn_register base,
507 int offset,
508 enum aarch64_insn_variant variant,
509 enum aarch64_insn_ldst_type type);
510u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
511 enum aarch64_insn_register base,
512 enum aarch64_insn_register state,
513 enum aarch64_insn_size_type size,
514 enum aarch64_insn_ldst_type type);
515u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
516 enum aarch64_insn_register src,
517 int imm, enum aarch64_insn_variant variant,
518 enum aarch64_insn_adsb_type type);
519u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
520 enum aarch64_insn_register reg,
521 enum aarch64_insn_adr_type type);
522u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
523 enum aarch64_insn_register src,
524 int immr, int imms,
525 enum aarch64_insn_variant variant,
526 enum aarch64_insn_bitfield_type type);
527u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
528 int imm, int shift,
529 enum aarch64_insn_variant variant,
530 enum aarch64_insn_movewide_type type);
531u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
532 enum aarch64_insn_register src,
533 enum aarch64_insn_register reg,
534 int shift,
535 enum aarch64_insn_variant variant,
536 enum aarch64_insn_adsb_type type);
537u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
538 enum aarch64_insn_register src,
539 enum aarch64_insn_variant variant,
540 enum aarch64_insn_data1_type type);
541u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
542 enum aarch64_insn_register src,
543 enum aarch64_insn_register reg,
544 enum aarch64_insn_variant variant,
545 enum aarch64_insn_data2_type type);
546u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
547 enum aarch64_insn_register src,
548 enum aarch64_insn_register reg1,
549 enum aarch64_insn_register reg2,
550 enum aarch64_insn_variant variant,
551 enum aarch64_insn_data3_type type);
552u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
553 enum aarch64_insn_register src,
554 enum aarch64_insn_register reg,
555 int shift,
556 enum aarch64_insn_variant variant,
557 enum aarch64_insn_logic_type type);
558u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
559 enum aarch64_insn_register src,
560 enum aarch64_insn_variant variant);
561u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
562 enum aarch64_insn_variant variant,
563 enum aarch64_insn_register Rn,
564 enum aarch64_insn_register Rd,
565 u64 imm);
566u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
567 enum aarch64_insn_register Rm,
568 enum aarch64_insn_register Rn,
569 enum aarch64_insn_register Rd,
570 u8 lsb);
571u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
572 enum aarch64_insn_prfm_type type,
573 enum aarch64_insn_prfm_target target,
574 enum aarch64_insn_prfm_policy policy);
575#ifdef CONFIG_ARM64_LSE_ATOMICS
576u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
577 enum aarch64_insn_register address,
578 enum aarch64_insn_register value,
579 enum aarch64_insn_size_type size,
580 enum aarch64_insn_mem_atomic_op op,
581 enum aarch64_insn_mem_order_type order);
582u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
583 enum aarch64_insn_register address,
584 enum aarch64_insn_register value,
585 enum aarch64_insn_size_type size,
586 enum aarch64_insn_mem_order_type order);
587#else
588static inline
589u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
590 enum aarch64_insn_register address,
591 enum aarch64_insn_register value,
592 enum aarch64_insn_size_type size,
593 enum aarch64_insn_mem_atomic_op op,
594 enum aarch64_insn_mem_order_type order)
595{
596 return AARCH64_BREAK_FAULT;
597}
598
599static inline
600u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
601 enum aarch64_insn_register address,
602 enum aarch64_insn_register value,
603 enum aarch64_insn_size_type size,
604 enum aarch64_insn_mem_order_type order)
605{
606 return AARCH64_BREAK_FAULT;
607}
608#endif
609u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
610
611s32 aarch64_get_branch_offset(u32 insn);
612u32 aarch64_set_branch_offset(u32 insn, s32 offset);
613
614s32 aarch64_insn_adrp_get_offset(u32 insn);
615u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
616
617bool aarch32_insn_is_wide(u32 insn);
618
619#define A32_RN_OFFSET 16
620#define A32_RT_OFFSET 12
621#define A32_RT2_OFFSET 0
622
623u32 aarch64_insn_extract_system_reg(u32 insn);
624u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
625u32 aarch32_insn_mcr_extract_opc2(u32 insn);
626u32 aarch32_insn_mcr_extract_crm(u32 insn);
627
628typedef bool (pstate_check_t)(unsigned long);
629extern pstate_check_t * const aarch32_opcode_cond_checks[16];
630
631#endif /* __ASSEMBLY__ */
632
633#endif /* __ASM_INSN_H */