tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8660.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 model = "Qualcomm MSM8660";
13 compatible = "qcom,msm8660";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "qcom,scorpion";
22 enable-method = "qcom,gcc-msm8660";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 };
27
28 cpu@1 {
29 compatible = "qcom,scorpion";
30 enable-method = "qcom,gcc-msm8660";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 };
35
36 L2: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <0x0 0x0>;
45 };
46
47 cpu-pmu {
48 compatible = "qcom,scorpion-mp-pmu";
49 interrupts = <1 9 0x304>;
50 };
51
52 clocks {
53 cxo_board {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <19200000>;
57 };
58
59 pxo_board {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 };
64
65 sleep_clk {
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <32768>;
69 };
70 };
71
72 /*
73 * These channels from the ADC are simply hardware monitors.
74 * That is why the ADC is referred to as "HKADC" - HouseKeeping
75 * ADC.
76 */
77 iio-hwmon {
78 compatible = "iio-hwmon";
79 io-channels = <&xoadc 0x00 0x01>, /* Battery */
80 <&xoadc 0x00 0x02>, /* DC in (charger) */
81 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
82 <&xoadc 0x00 0x0b>, /* Die temperature */
83 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
84 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
85 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
86 };
87
88 soc: soc {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92 compatible = "simple-bus";
93
94 intc: interrupt-controller@2080000 {
95 compatible = "qcom,msm-8660-qgic";
96 interrupt-controller;
97 #interrupt-cells = <3>;
98 reg = < 0x02080000 0x1000 >,
99 < 0x02081000 0x1000 >;
100 };
101
102 timer@2000000 {
103 compatible = "qcom,scss-timer", "qcom,msm-timer";
104 interrupts = <1 0 0x301>,
105 <1 1 0x301>,
106 <1 2 0x301>;
107 reg = <0x02000000 0x100>;
108 clock-frequency = <27000000>,
109 <32768>;
110 cpu-offset = <0x40000>;
111 };
112
113 tlmm: pinctrl@800000 {
114 compatible = "qcom,msm8660-pinctrl";
115 reg = <0x800000 0x4000>;
116
117 gpio-controller;
118 gpio-ranges = <&tlmm 0 0 173>;
119 #gpio-cells = <2>;
120 interrupts = <0 16 0x4>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
123
124 };
125
126 gcc: clock-controller@900000 {
127 compatible = "qcom,gcc-msm8660";
128 #clock-cells = <1>;
129 #power-domain-cells = <1>;
130 #reset-cells = <1>;
131 reg = <0x900000 0x4000>;
132 };
133
134 gsbi6: gsbi@16500000 {
135 compatible = "qcom,gsbi-v1.0.0";
136 cell-index = <12>;
137 reg = <0x16500000 0x100>;
138 clocks = <&gcc GSBI6_H_CLK>;
139 clock-names = "iface";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges;
143 status = "disabled";
144
145 syscon-tcsr = <&tcsr>;
146
147 gsbi6_serial: serial@16540000 {
148 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
149 reg = <0x16540000 0x1000>,
150 <0x16500000 0x1000>;
151 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
153 clock-names = "core", "iface";
154 status = "disabled";
155 };
156
157 gsbi6_i2c: i2c@16580000 {
158 compatible = "qcom,i2c-qup-v1.1.1";
159 reg = <0x16580000 0x1000>;
160 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
162 clock-names = "core", "iface";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 status = "disabled";
166 };
167 };
168
169 gsbi7: gsbi@16600000 {
170 compatible = "qcom,gsbi-v1.0.0";
171 cell-index = <12>;
172 reg = <0x16600000 0x100>;
173 clocks = <&gcc GSBI7_H_CLK>;
174 clock-names = "iface";
175 #address-cells = <1>;
176 #size-cells = <1>;
177 ranges;
178 status = "disabled";
179
180 syscon-tcsr = <&tcsr>;
181
182 gsbi7_serial: serial@16640000 {
183 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
184 reg = <0x16640000 0x1000>,
185 <0x16600000 0x1000>;
186 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
188 clock-names = "core", "iface";
189 status = "disabled";
190 };
191
192 gsbi7_i2c: i2c@16680000 {
193 compatible = "qcom,i2c-qup-v1.1.1";
194 reg = <0x16680000 0x1000>;
195 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
197 clock-names = "core", "iface";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 status = "disabled";
201 };
202 };
203
204 gsbi8: gsbi@19800000 {
205 compatible = "qcom,gsbi-v1.0.0";
206 cell-index = <12>;
207 reg = <0x19800000 0x100>;
208 clocks = <&gcc GSBI8_H_CLK>;
209 clock-names = "iface";
210 #address-cells = <1>;
211 #size-cells = <1>;
212 ranges;
213
214 syscon-tcsr = <&tcsr>;
215
216 gsbi8_i2c: i2c@19880000 {
217 compatible = "qcom,i2c-qup-v1.1.1";
218 reg = <0x19880000 0x1000>;
219 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
221 clock-names = "core", "iface";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 status = "disabled";
225 };
226 };
227
228 gsbi12: gsbi@19c00000 {
229 compatible = "qcom,gsbi-v1.0.0";
230 cell-index = <12>;
231 reg = <0x19c00000 0x100>;
232 clocks = <&gcc GSBI12_H_CLK>;
233 clock-names = "iface";
234 #address-cells = <1>;
235 #size-cells = <1>;
236 ranges;
237
238 syscon-tcsr = <&tcsr>;
239
240 gsbi12_serial: serial@19c40000 {
241 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
242 reg = <0x19c40000 0x1000>,
243 <0x19c00000 0x1000>;
244 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
246 clock-names = "core", "iface";
247 status = "disabled";
248 };
249
250 gsbi12_i2c: i2c@19c80000 {
251 compatible = "qcom,i2c-qup-v1.1.1";
252 reg = <0x19c80000 0x1000>;
253 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
255 clock-names = "core", "iface";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 status = "disabled";
259 };
260 };
261
262 external-bus@1a100000 {
263 compatible = "qcom,msm8660-ebi2";
264 #address-cells = <2>;
265 #size-cells = <1>;
266 ranges = <0 0x0 0x1a800000 0x00800000>,
267 <1 0x0 0x1b000000 0x00800000>,
268 <2 0x0 0x1b800000 0x00800000>,
269 <3 0x0 0x1d000000 0x08000000>,
270 <4 0x0 0x1c800000 0x00800000>,
271 <5 0x0 0x1c000000 0x00800000>;
272 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
273 reg-names = "ebi2", "xmem";
274 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
275 clock-names = "ebi2x", "ebi2";
276 status = "disabled";
277 };
278
279 qcom,ssbi@500000 {
280 compatible = "qcom,ssbi";
281 reg = <0x500000 0x1000>;
282 qcom,controller-type = "pmic-arbiter";
283
284 pm8058: pmic@0 {
285 compatible = "qcom,pm8058";
286 interrupt-parent = <&tlmm>;
287 interrupts = <88 8>;
288 #interrupt-cells = <2>;
289 interrupt-controller;
290 #address-cells = <1>;
291 #size-cells = <0>;
292
293 pm8058_gpio: gpio@150 {
294 compatible = "qcom,pm8058-gpio",
295 "qcom,ssbi-gpio";
296 reg = <0x150>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 gpio-controller;
300 gpio-ranges = <&pm8058_gpio 0 0 44>;
301 #gpio-cells = <2>;
302
303 };
304
305 pm8058_mpps: mpps@50 {
306 compatible = "qcom,pm8058-mpp",
307 "qcom,ssbi-mpp";
308 reg = <0x50>;
309 gpio-controller;
310 #gpio-cells = <2>;
311 gpio-ranges = <&pm8058_mpps 0 0 12>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315
316 pwrkey@1c {
317 compatible = "qcom,pm8058-pwrkey";
318 reg = <0x1c>;
319 interrupt-parent = <&pm8058>;
320 interrupts = <50 1>, <51 1>;
321 debounce = <15625>;
322 pull-up;
323 };
324
325 keypad@148 {
326 compatible = "qcom,pm8058-keypad";
327 reg = <0x148>;
328 interrupt-parent = <&pm8058>;
329 interrupts = <74 1>, <75 1>;
330 debounce = <15>;
331 scan-delay = <32>;
332 row-hold = <91500>;
333 };
334
335 xoadc: xoadc@197 {
336 compatible = "qcom,pm8058-adc";
337 reg = <0x197>;
338 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
339 #address-cells = <2>;
340 #size-cells = <0>;
341 #io-channel-cells = <2>;
342
343 vcoin: adc-channel@0 {
344 reg = <0x00 0x00>;
345 };
346 vbat: adc-channel@1 {
347 reg = <0x00 0x01>;
348 };
349 dcin: adc-channel@2 {
350 reg = <0x00 0x02>;
351 };
352 ichg: adc-channel@3 {
353 reg = <0x00 0x03>;
354 };
355 vph_pwr: adc-channel@4 {
356 reg = <0x00 0x04>;
357 };
358 usb_vbus: adc-channel@a {
359 reg = <0x00 0x0a>;
360 };
361 die_temp: adc-channel@b {
362 reg = <0x00 0x0b>;
363 };
364 ref_625mv: adc-channel@c {
365 reg = <0x00 0x0c>;
366 };
367 ref_1250mv: adc-channel@d {
368 reg = <0x00 0x0d>;
369 };
370 ref_325mv: adc-channel@e {
371 reg = <0x00 0x0e>;
372 };
373 ref_muxoff: adc-channel@f {
374 reg = <0x00 0x0f>;
375 };
376 };
377
378 rtc@1e8 {
379 compatible = "qcom,pm8058-rtc";
380 reg = <0x1e8>;
381 interrupt-parent = <&pm8058>;
382 interrupts = <39 1>;
383 allow-set-time;
384 };
385
386 vibrator@4a {
387 compatible = "qcom,pm8058-vib";
388 reg = <0x4a>;
389 };
390 };
391 };
392
393 l2cc: clock-controller@2082000 {
394 compatible = "qcom,kpss-gcc", "syscon";
395 reg = <0x02082000 0x1000>;
396 };
397
398 rpm: rpm@104000 {
399 compatible = "qcom,rpm-msm8660";
400 reg = <0x00104000 0x1000>;
401 qcom,ipc = <&l2cc 0x8 2>;
402
403 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
404 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
405 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
406 interrupt-names = "ack", "err", "wakeup";
407 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
408 clock-names = "ram";
409
410 rpmcc: clock-controller {
411 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
412 #clock-cells = <1>;
413 };
414
415 pm8901-regulators {
416 compatible = "qcom,rpm-pm8901-regulators";
417
418 pm8901_l0: l0 {};
419 pm8901_l1: l1 {};
420 pm8901_l2: l2 {};
421 pm8901_l3: l3 {};
422 pm8901_l4: l4 {};
423 pm8901_l5: l5 {};
424 pm8901_l6: l6 {};
425
426 /* S0 and S1 Handled as SAW regulators by SPM */
427 pm8901_s2: s2 {};
428 pm8901_s3: s3 {};
429 pm8901_s4: s4 {};
430
431 pm8901_lvs0: lvs0 {};
432 pm8901_lvs1: lvs1 {};
433 pm8901_lvs2: lvs2 {};
434 pm8901_lvs3: lvs3 {};
435
436 pm8901_mvs: mvs {};
437 };
438
439 pm8058-regulators {
440 compatible = "qcom,rpm-pm8058-regulators";
441
442 pm8058_l0: l0 {};
443 pm8058_l1: l1 {};
444 pm8058_l2: l2 {};
445 pm8058_l3: l3 {};
446 pm8058_l4: l4 {};
447 pm8058_l5: l5 {};
448 pm8058_l6: l6 {};
449 pm8058_l7: l7 {};
450 pm8058_l8: l8 {};
451 pm8058_l9: l9 {};
452 pm8058_l10: l10 {};
453 pm8058_l11: l11 {};
454 pm8058_l12: l12 {};
455 pm8058_l13: l13 {};
456 pm8058_l14: l14 {};
457 pm8058_l15: l15 {};
458 pm8058_l16: l16 {};
459 pm8058_l17: l17 {};
460 pm8058_l18: l18 {};
461 pm8058_l19: l19 {};
462 pm8058_l20: l20 {};
463 pm8058_l21: l21 {};
464 pm8058_l22: l22 {};
465 pm8058_l23: l23 {};
466 pm8058_l24: l24 {};
467 pm8058_l25: l25 {};
468
469 pm8058_s0: s0 {};
470 pm8058_s1: s1 {};
471 pm8058_s2: s2 {};
472 pm8058_s3: s3 {};
473 pm8058_s4: s4 {};
474
475 pm8058_lvs0: lvs0 {};
476 pm8058_lvs1: lvs1 {};
477
478 pm8058_ncp: ncp {};
479 };
480 };
481
482 amba {
483 compatible = "simple-bus";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges;
487 sdcc1: mmc@12400000 {
488 status = "disabled";
489 compatible = "arm,pl18x", "arm,primecell";
490 arm,primecell-periphid = <0x00051180>;
491 reg = <0x12400000 0x8000>;
492 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
493 interrupt-names = "cmd_irq";
494 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
495 clock-names = "mclk", "apb_pclk";
496 bus-width = <8>;
497 max-frequency = <48000000>;
498 non-removable;
499 cap-sd-highspeed;
500 cap-mmc-highspeed;
501 };
502
503 sdcc2: mmc@12140000 {
504 status = "disabled";
505 compatible = "arm,pl18x", "arm,primecell";
506 arm,primecell-periphid = <0x00051180>;
507 reg = <0x12140000 0x8000>;
508 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "cmd_irq";
510 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
511 clock-names = "mclk", "apb_pclk";
512 bus-width = <8>;
513 max-frequency = <48000000>;
514 cap-sd-highspeed;
515 cap-mmc-highspeed;
516 };
517
518 sdcc3: mmc@12180000 {
519 compatible = "arm,pl18x", "arm,primecell";
520 arm,primecell-periphid = <0x00051180>;
521 status = "disabled";
522 reg = <0x12180000 0x8000>;
523 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
524 interrupt-names = "cmd_irq";
525 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
526 clock-names = "mclk", "apb_pclk";
527 bus-width = <4>;
528 cap-sd-highspeed;
529 cap-mmc-highspeed;
530 max-frequency = <48000000>;
531 no-1-8-v;
532 };
533
534 sdcc4: mmc@121c0000 {
535 compatible = "arm,pl18x", "arm,primecell";
536 arm,primecell-periphid = <0x00051180>;
537 status = "disabled";
538 reg = <0x121c0000 0x8000>;
539 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
540 interrupt-names = "cmd_irq";
541 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
542 clock-names = "mclk", "apb_pclk";
543 bus-width = <4>;
544 max-frequency = <48000000>;
545 cap-sd-highspeed;
546 cap-mmc-highspeed;
547 };
548
549 sdcc5: mmc@12200000 {
550 compatible = "arm,pl18x", "arm,primecell";
551 arm,primecell-periphid = <0x00051180>;
552 status = "disabled";
553 reg = <0x12200000 0x8000>;
554 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
555 interrupt-names = "cmd_irq";
556 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
557 clock-names = "mclk", "apb_pclk";
558 bus-width = <4>;
559 cap-sd-highspeed;
560 cap-mmc-highspeed;
561 max-frequency = <48000000>;
562 };
563 };
564
565 tcsr: syscon@1a400000 {
566 compatible = "qcom,tcsr-msm8660", "syscon";
567 reg = <0x1a400000 0x100>;
568 };
569 };
570
571};