tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19 model = "Turris Omnia";
20 compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22 chosen {
23 stdout-path = &uart0;
24 };
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x40000000>; /* 1024 MB */
29 };
30
31 soc {
32 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
33 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
34 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
35 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
36 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
37
38 internal-regs {
39
40 /* USB part of the PCIe2/USB 2.0 port */
41 usb@58000 {
42 status = "okay";
43 };
44
45 sata@a8000 {
46 status = "okay";
47 };
48
49 sdhci@d8000 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&sdhci_pins>;
52 status = "okay";
53
54 bus-width = <8>;
55 no-1-8-v;
56 non-removable;
57 };
58
59 usb3@f0000 {
60 status = "okay";
61 };
62
63 usb3@f8000 {
64 status = "okay";
65 };
66 };
67
68 pcie {
69 status = "okay";
70
71 pcie@1,0 {
72 /* Port 0, Lane 0 */
73 status = "okay";
74 slot-power-limit-milliwatt = <10000>;
75 };
76
77 pcie@2,0 {
78 /* Port 1, Lane 0 */
79 status = "okay";
80 slot-power-limit-milliwatt = <10000>;
81 };
82
83 pcie@3,0 {
84 /* Port 2, Lane 0 */
85 status = "okay";
86 slot-power-limit-milliwatt = <10000>;
87 };
88 };
89 };
90
91 sfp: sfp {
92 compatible = "sff,sfp";
93 i2c-bus = <&sfp_i2c>;
94 tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
95 tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
96 rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
97 los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
98 mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
99 maximum-power-milliwatt = <3000>;
100
101 /*
102 * For now this has to be enabled at boot time by U-Boot when
103 * a SFP module is present. Read more in the comment in the
104 * eth2 node below.
105 */
106 status = "disabled";
107 };
108};
109
110&bm {
111 status = "okay";
112};
113
114&bm_bppi {
115 status = "okay";
116};
117
118/* Connected to 88E6176 switch, port 6 */
119ð0 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&ge0_rgmii_pins>;
122 status = "okay";
123 phy-mode = "rgmii";
124 buffer-manager = <&bm>;
125 bm,pool-long = <0>;
126 bm,pool-short = <3>;
127
128 fixed-link {
129 speed = <1000>;
130 full-duplex;
131 };
132};
133
134/* Connected to 88E6176 switch, port 5 */
135ð1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&ge1_rgmii_pins>;
138 status = "okay";
139 phy-mode = "rgmii";
140 buffer-manager = <&bm>;
141 bm,pool-long = <1>;
142 bm,pool-short = <3>;
143
144 fixed-link {
145 speed = <1000>;
146 full-duplex;
147 };
148};
149
150/* WAN port */
151ð2 {
152 /*
153 * eth2 is connected via a multiplexor to both the SFP cage and to
154 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
155 * a SFP module is present, as determined by the mode-def0 GPIO.
156 *
157 * Until kernel supports this configuration properly, in case SFP module
158 * is present, U-Boot has to enable the sfp node above, remove phy
159 * handle and add managed = "in-band-status" property.
160 */
161 status = "okay";
162 phy-mode = "sgmii";
163 phy-handle = <&phy1>;
164 phys = <&comphy5 2>;
165 sfp = <&sfp>;
166 buffer-manager = <&bm>;
167 bm,pool-long = <2>;
168 bm,pool-short = <3>;
169};
170
171&i2c0 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&i2c0_pins>;
174 status = "okay";
175
176 i2cmux@70 {
177 compatible = "nxp,pca9547";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 reg = <0x70>;
181
182 i2c@0 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 reg = <0>;
186
187 /* STM32F0 command interface at address 0x2a */
188
189 led-controller@2b {
190 compatible = "cznic,turris-omnia-leds";
191 reg = <0x2b>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 /*
196 * LEDs are controlled by MCU (STM32F0) at
197 * address 0x2b.
198 *
199 * The driver does not support HW control mode
200 * for the LEDs yet. Disable the LEDs for now.
201 *
202 * Also LED functions are not stable yet:
203 * - there are 3 LEDs connected via MCU to PCIe
204 * ports. One of these ports supports mSATA.
205 * There is no mSATA nor PCIe function.
206 * For now we use LED_FUNCTION_WLAN, since
207 * in most cases users have wifi cards in
208 * these slots
209 * - there are 2 LEDs dedicated for user: A and
210 * B. Again there is no such function defined.
211 * For now we use LED_FUNCTION_INDICATOR
212 */
213 status = "disabled";
214
215 multi-led@0 {
216 reg = <0x0>;
217 color = <LED_COLOR_ID_RGB>;
218 function = LED_FUNCTION_INDICATOR;
219 function-enumerator = <2>;
220 };
221
222 multi-led@1 {
223 reg = <0x1>;
224 color = <LED_COLOR_ID_RGB>;
225 function = LED_FUNCTION_INDICATOR;
226 function-enumerator = <1>;
227 };
228
229 multi-led@2 {
230 reg = <0x2>;
231 color = <LED_COLOR_ID_RGB>;
232 function = LED_FUNCTION_WLAN;
233 function-enumerator = <3>;
234 };
235
236 multi-led@3 {
237 reg = <0x3>;
238 color = <LED_COLOR_ID_RGB>;
239 function = LED_FUNCTION_WLAN;
240 function-enumerator = <2>;
241 };
242
243 multi-led@4 {
244 reg = <0x4>;
245 color = <LED_COLOR_ID_RGB>;
246 function = LED_FUNCTION_WLAN;
247 function-enumerator = <1>;
248 };
249
250 multi-led@5 {
251 reg = <0x5>;
252 color = <LED_COLOR_ID_RGB>;
253 function = LED_FUNCTION_WAN;
254 };
255
256 multi-led@6 {
257 reg = <0x6>;
258 color = <LED_COLOR_ID_RGB>;
259 function = LED_FUNCTION_LAN;
260 function-enumerator = <4>;
261 };
262
263 multi-led@7 {
264 reg = <0x7>;
265 color = <LED_COLOR_ID_RGB>;
266 function = LED_FUNCTION_LAN;
267 function-enumerator = <3>;
268 };
269
270 multi-led@8 {
271 reg = <0x8>;
272 color = <LED_COLOR_ID_RGB>;
273 function = LED_FUNCTION_LAN;
274 function-enumerator = <2>;
275 };
276
277 multi-led@9 {
278 reg = <0x9>;
279 color = <LED_COLOR_ID_RGB>;
280 function = LED_FUNCTION_LAN;
281 function-enumerator = <1>;
282 };
283
284 multi-led@a {
285 reg = <0xa>;
286 color = <LED_COLOR_ID_RGB>;
287 function = LED_FUNCTION_LAN;
288 function-enumerator = <0>;
289 };
290
291 multi-led@b {
292 reg = <0xb>;
293 color = <LED_COLOR_ID_RGB>;
294 function = LED_FUNCTION_POWER;
295 };
296 };
297
298 eeprom@54 {
299 compatible = "atmel,24c64";
300 reg = <0x54>;
301
302 /* The EEPROM contains data for bootloader.
303 * Contents:
304 * struct omnia_eeprom {
305 * u32 magic; (=0x0341a034 in LE)
306 * u32 ramsize; (in GiB)
307 * char regdomain[4];
308 * u32 crc32;
309 * };
310 */
311 };
312 };
313
314 i2c@1 {
315 #address-cells = <1>;
316 #size-cells = <0>;
317 reg = <1>;
318
319 /* routed to PCIe0/mSATA connector (CN7A) */
320 };
321
322 i2c@2 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 reg = <2>;
326
327 /* routed to PCIe1/USB2 connector (CN61A) */
328 };
329
330 i2c@3 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 reg = <3>;
334
335 /* routed to PCIe2 connector (CN62A) */
336 };
337
338 sfp_i2c: i2c@4 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 reg = <4>;
342
343 /* routed to SFP+ */
344 };
345
346 i2c@5 {
347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <5>;
350
351 /* ATSHA204A at address 0x64 */
352 };
353
354 i2c@6 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 reg = <6>;
358
359 /* exposed on pin header */
360 };
361
362 i2c@7 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <7>;
366
367 pcawan: gpio@71 {
368 /*
369 * GPIO expander for SFP+ signals and
370 * and phy irq
371 */
372 compatible = "nxp,pca9538";
373 reg = <0x71>;
374
375 pinctrl-names = "default";
376 pinctrl-0 = <&pcawan_pins>;
377
378 interrupt-parent = <&gpio1>;
379 interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
380
381 gpio-controller;
382 #gpio-cells = <2>;
383 };
384 };
385 };
386};
387
388&mdio {
389 pinctrl-names = "default";
390 pinctrl-0 = <&mdio_pins>;
391 status = "okay";
392
393 phy1: ethernet-phy@1 {
394 compatible = "ethernet-phy-ieee802.3-c22";
395 reg = <1>;
396 marvell,reg-init = <3 18 0 0x4985>;
397
398 /* irq is connected to &pcawan pin 7 */
399 };
400
401 /* Switch MV88E6176 at address 0x10 */
402 switch@10 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&swint_pins>;
405 compatible = "marvell,mv88e6085";
406 #address-cells = <1>;
407 #size-cells = <0>;
408
409 dsa,member = <0 0>;
410 reg = <0x10>;
411
412 interrupt-parent = <&gpio1>;
413 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
414
415 ports {
416 #address-cells = <1>;
417 #size-cells = <0>;
418
419 ports@0 {
420 reg = <0>;
421 label = "lan0";
422 };
423
424 ports@1 {
425 reg = <1>;
426 label = "lan1";
427 };
428
429 ports@2 {
430 reg = <2>;
431 label = "lan2";
432 };
433
434 ports@3 {
435 reg = <3>;
436 label = "lan3";
437 };
438
439 ports@4 {
440 reg = <4>;
441 label = "lan4";
442 };
443
444 ports@5 {
445 reg = <5>;
446 label = "cpu";
447 ethernet = <ð1>;
448 phy-mode = "rgmii-id";
449
450 fixed-link {
451 speed = <1000>;
452 full-duplex;
453 };
454 };
455
456 /* port 6 is connected to eth0 */
457 };
458 };
459};
460
461&pinctrl {
462 pcawan_pins: pcawan-pins {
463 marvell,pins = "mpp46";
464 marvell,function = "gpio";
465 };
466
467 swint_pins: swint-pins {
468 marvell,pins = "mpp45";
469 marvell,function = "gpio";
470 };
471
472 spi0cs0_pins: spi0cs0-pins {
473 marvell,pins = "mpp25";
474 marvell,function = "spi0";
475 };
476
477 spi0cs1_pins: spi0cs1-pins {
478 marvell,pins = "mpp26";
479 marvell,function = "spi0";
480 };
481};
482
483&spi0 {
484 pinctrl-names = "default";
485 pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
486 status = "okay";
487
488 spi-nor@0 {
489 compatible = "spansion,s25fl164k", "jedec,spi-nor";
490 #address-cells = <1>;
491 #size-cells = <1>;
492 reg = <0>;
493 spi-max-frequency = <40000000>;
494
495 partitions {
496 compatible = "fixed-partitions";
497 #address-cells = <1>;
498 #size-cells = <1>;
499
500 partition@0 {
501 reg = <0x0 0x00100000>;
502 label = "U-Boot";
503 };
504
505 partition@100000 {
506 reg = <0x00100000 0x00700000>;
507 label = "Rescue system";
508 };
509 };
510 };
511
512 /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
513};
514
515&uart0 {
516 /* Pin header CN10 */
517 pinctrl-names = "default";
518 pinctrl-0 = <&uart0_pins>;
519 status = "okay";
520};
521
522&uart1 {
523 /* Pin header CN11 */
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart1_pins>;
526 status = "okay";
527};