tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
3
4/* Based on code by myc_c335x.dts, MYiRtech.com */
5/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
6
7/dts-v1/;
8
9#include "am33xx.dtsi"
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/leds/common.h>
13
14/ {
15 model = "MYIR MYC-AM335X";
16 compatible = "myir,myc-am335x", "ti,am33xx";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&vdd_core>;
21 voltage-tolerance = <2>;
22 };
23 };
24
25 memory@80000000 {
26 device_type = "memory";
27 reg = <0x80000000 0x10000000>;
28 };
29
30 vdd_mod: vdd_mod_reg {
31 compatible = "regulator-fixed";
32 regulator-name = "vdd-mod";
33 regulator-always-on;
34 regulator-boot-on;
35 };
36
37 vdd_core: vdd_core_reg {
38 compatible = "regulator-fixed";
39 regulator-name = "vdd-core";
40 regulator-always-on;
41 regulator-boot-on;
42 vin-supply = <&vdd_mod>;
43 };
44
45 leds: leds {
46 compatible = "gpio-leds";
47 pinctrl-names = "default";
48 pinctrl-0 = <&led_mod_pins>;
49
50 led_mod: led_mod {
51 label = "module:user";
52 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
53 color = <LED_COLOR_ID_GREEN>;
54 default-state = "off";
55 panic-indicator;
56 };
57 };
58};
59
60&mac_sw {
61 pinctrl-names = "default", "sleep";
62 pinctrl-0 = <ð_slave1_pins_default>;
63 pinctrl-1 = <ð_slave1_pins_sleep>;
64 status = "okay";
65};
66
67&cpsw_port1 {
68 phy-handle = <&phy0>;
69 phy-mode = "rgmii-id";
70 ti,dual-emac-pvid = <1>;
71};
72
73&cpsw_port2 {
74 status = "disabled";
75};
76
77&davinci_mdio_sw {
78 pinctrl-names = "default", "sleep";
79 pinctrl-0 = <&mdio_pins_default>;
80 pinctrl-1 = <&mdio_pins_sleep>;
81
82 phy0: ethernet-phy@4 {
83 reg = <4>;
84 };
85};
86
87&elm {
88 status = "okay";
89};
90
91&gpmc {
92 pinctrl-names = "default", "sleep";
93 pinctrl-0 = <&nand_pins_default>;
94 pinctrl-1 = <&nand_pins_sleep>;
95 ranges = <0 0 0x8000000 0x1000000>;
96 status = "okay";
97
98 nand0: nand@0,0 {
99 compatible = "ti,omap2-nand";
100 reg = <0 0 4>;
101 interrupt-parent = <&gpmc>;
102 interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE_NONE>;
103 nand-bus-width = <8>;
104 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;
105 gpmc,device-width = <1>;
106 gpmc,sync-clk-ps = <0>;
107 gpmc,cs-on-ns = <0>;
108 gpmc,cs-rd-off-ns = <44>;
109 gpmc,cs-wr-off-ns = <44>;
110 gpmc,adv-on-ns = <6>;
111 gpmc,adv-rd-off-ns = <34>;
112 gpmc,adv-wr-off-ns = <44>;
113 gpmc,we-on-ns = <0>;
114 gpmc,we-off-ns = <40>;
115 gpmc,oe-on-ns = <0>;
116 gpmc,oe-off-ns = <54>;
117 gpmc,access-ns = <64>;
118 gpmc,rd-cycle-ns = <82>;
119 gpmc,wr-cycle-ns = <82>;
120 gpmc,bus-turnaround-ns = <0>;
121 gpmc,cycle2cycle-delay-ns = <0>;
122 gpmc,clk-activation-ns = <0>;
123 gpmc,wr-access-ns = <40>;
124 gpmc,wr-data-mux-bus-ns = <0>;
125 ti,elm-id = <&elm>;
126 ti,nand-ecc-opt = "bch8";
127
128 #address-cells = <1>;
129 #size-cells = <1>;
130 };
131};
132
133&i2c0 {
134 pinctrl-names = "default", "gpio", "sleep";
135 pinctrl-0 = <&i2c0_pins_default>;
136 pinctrl-1 = <&i2c0_pins_gpio>;
137 pinctrl-2 = <&i2c0_pins_sleep>;
138 clock-frequency = <400000>;
139 scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
140 sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
141 status = "okay";
142
143 eeprom: eeprom@50 {
144 compatible = "atmel,24c32";
145 reg = <0x50>;
146 pagesize = <32>;
147 vcc-supply = <&vdd_mod>;
148 };
149};
150
151&rtc {
152 system-power-controller;
153};
154
155&am33xx_pinmux {
156 mdio_pins_default: pinmux_mdio_pins_default {
157 pinctrl-single,pins = <
158 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) /* mdio_data */
159 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) /* mdio_clk */
160 >;
161 };
162
163 mdio_pins_sleep: pinmux_mdio_pins_sleep {
164 pinctrl-single,pins = <
165 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
166 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
167 >;
168 };
169
170 eth_slave1_pins_default: pinmux_eth_slave1_pins_default {
171 pinctrl-single,pins = <
172 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tctl */
173 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rctl */
174 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td3 */
175 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td2 */
176 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td1 */
177 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_td0 */
178 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii1_tclk */
179 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rclk */
180 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd3 */
181 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd2 */
182 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd1 */
183 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii1_rd0 */
184 >;
185 };
186
187 eth_slave1_pins_sleep: pinmux_eth_slave1_pins_sleep {
188 pinctrl-single,pins = <
189 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
190 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
191 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
192 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
193 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
194 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
195 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
196 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
197 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
198 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
199 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
200 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
201 >;
202 };
203
204 i2c0_pins_default: pinmux_i2c0_pins_default {
205 pinctrl-single,pins = <
206 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SDA */
207 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE0) /* I2C0_SCL */
208 >;
209 };
210
211 i2c0_pins_gpio: pinmux_i2c0_pins_gpio {
212 pinctrl-single,pins = <
213 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE7) /* gpio3[5] */
214 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE7) /* gpio3[6] */
215 >;
216 };
217
218 i2c0_pins_sleep: pinmux_i2c0_pins_sleep {
219 pinctrl-single,pins = <
220 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE7)
221 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE7)
222 >;
223 };
224
225 led_mod_pins: pinmux_led_mod_pins {
226 pinctrl-single,pins = <
227 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpio3[18] */
228 >;
229 };
230
231 nand_pins_default: pinmux_nand_pins_default {
232 pinctrl-single,pins = <
233 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad0 */
234 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad1 */
235 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad2 */
236 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad3 */
237 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad4 */
238 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad5 */
239 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6 */
240 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7 */
241 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0 */
242 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio0[31] */
243 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0 */
244 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale */
245 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren */
246 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) /* gpmc_wen */
247 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) /* gpmc_be0n_cle */
248 >;
249 };
250
251 nand_pins_sleep: pinmux_nand_pins_sleep {
252 pinctrl-single,pins = <
253 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
254 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
255 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
256 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
257 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE7)
258 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE7)
259 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE7)
260 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE7)
261 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)
262 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)
263 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT_PULLDOWN, MUX_MODE7)
264 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)
265 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)
266 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT_PULLDOWN, MUX_MODE7)
267 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)
268 >;
269 };
270};