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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10 - Weiyi Lu <weiyi.lu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
16
17 IP cores belonging to a power domain should contain a 'power-domains'
18 property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21 $nodename:
22 const: power-controller
23
24 compatible:
25 enum:
26 - mediatek,mt8167-power-controller
27 - mediatek,mt8173-power-controller
28 - mediatek,mt8183-power-controller
29 - mediatek,mt8186-power-controller
30 - mediatek,mt8192-power-controller
31 - mediatek,mt8195-power-controller
32
33 '#power-domain-cells':
34 const: 1
35
36 '#address-cells':
37 const: 1
38
39 '#size-cells':
40 const: 0
41
42patternProperties:
43 "^power-domain@[0-9a-f]+$":
44 type: object
45 description: |
46 Represents the power domains within the power controller node as documented
47 in Documentation/devicetree/bindings/power/power-domain.yaml.
48
49 properties:
50
51 '#power-domain-cells':
52 description:
53 Must be 0 for nodes representing a single PM domain and 1 for nodes
54 providing multiple PM domains.
55
56 '#address-cells':
57 const: 1
58
59 '#size-cells':
60 const: 0
61
62 reg:
63 description: |
64 Power domain index. Valid values are defined in:
65 "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
66 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
67 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
68 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
69 "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
70 maxItems: 1
71
72 clocks:
73 description: |
74 A number of phandles to clocks that need to be enabled during domain
75 power-up sequencing.
76
77 clock-names:
78 description: |
79 List of names of clocks, in order to match the power-up sequencing
80 for each power domain we need to group the clocks by name. BASIC
81 clocks need to be enabled before enabling the corresponding power
82 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
83 SUSBYS clocks need to be enabled before releasing the bus protection,
84 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
85
86 In order to follow properly the power-up sequencing, the clocks must
87 be specified by order, adding first the BASIC clocks followed by the
88 SUSBSYS clocks.
89
90 domain-supply:
91 description: domain regulator supply.
92
93 mediatek,infracfg:
94 $ref: /schemas/types.yaml#/definitions/phandle
95 description: phandle to the device containing the INFRACFG register range.
96
97 mediatek,smi:
98 $ref: /schemas/types.yaml#/definitions/phandle
99 description: phandle to the device containing the SMI register range.
100
101 patternProperties:
102 "^power-domain@[0-9a-f]+$":
103 type: object
104 description: |
105 Represents a power domain child within a power domain parent node.
106
107 properties:
108
109 '#power-domain-cells':
110 description:
111 Must be 0 for nodes representing a single PM domain and 1 for nodes
112 providing multiple PM domains.
113
114 '#address-cells':
115 const: 1
116
117 '#size-cells':
118 const: 0
119
120 reg:
121 maxItems: 1
122
123 clocks:
124 description: |
125 A number of phandles to clocks that need to be enabled during domain
126 power-up sequencing.
127
128 clock-names:
129 description: |
130 List of names of clocks, in order to match the power-up sequencing
131 for each power domain we need to group the clocks by name. BASIC
132 clocks need to be enabled before enabling the corresponding power
133 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
134 SUSBYS clocks need to be enabled before releasing the bus protection,
135 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
136
137 In order to follow properly the power-up sequencing, the clocks must
138 be specified by order, adding first the BASIC clocks followed by the
139 SUSBSYS clocks.
140
141 domain-supply:
142 description: domain regulator supply.
143
144 mediatek,infracfg:
145 $ref: /schemas/types.yaml#/definitions/phandle
146 description: phandle to the device containing the INFRACFG register range.
147
148 mediatek,smi:
149 $ref: /schemas/types.yaml#/definitions/phandle
150 description: phandle to the device containing the SMI register range.
151
152 patternProperties:
153 "^power-domain@[0-9a-f]+$":
154 type: object
155 description: |
156 Represents a power domain child within a power domain parent node.
157
158 properties:
159
160 '#power-domain-cells':
161 description:
162 Must be 0 for nodes representing a single PM domain and 1 for nodes
163 providing multiple PM domains.
164
165 '#address-cells':
166 const: 1
167
168 '#size-cells':
169 const: 0
170
171 reg:
172 maxItems: 1
173
174 clocks:
175 description: |
176 A number of phandles to clocks that need to be enabled during domain
177 power-up sequencing.
178
179 clock-names:
180 description: |
181 List of names of clocks, in order to match the power-up sequencing
182 for each power domain we need to group the clocks by name. BASIC
183 clocks need to be enabled before enabling the corresponding power
184 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
185 SUSBYS clocks need to be enabled before releasing the bus protection,
186 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
187
188 In order to follow properly the power-up sequencing, the clocks must
189 be specified by order, adding first the BASIC clocks followed by the
190 SUSBSYS clocks.
191
192 domain-supply:
193 description: domain regulator supply.
194
195 mediatek,infracfg:
196 $ref: /schemas/types.yaml#/definitions/phandle
197 description: phandle to the device containing the INFRACFG register range.
198
199 mediatek,smi:
200 $ref: /schemas/types.yaml#/definitions/phandle
201 description: phandle to the device containing the SMI register range.
202
203 required:
204 - reg
205
206 additionalProperties: false
207
208 required:
209 - reg
210
211 additionalProperties: false
212
213 required:
214 - reg
215
216 additionalProperties: false
217
218required:
219 - compatible
220
221additionalProperties: false
222
223examples:
224 - |
225 #include <dt-bindings/clock/mt8173-clk.h>
226 #include <dt-bindings/power/mt8173-power.h>
227
228 soc {
229 #address-cells = <2>;
230 #size-cells = <2>;
231
232 scpsys: syscon@10006000 {
233 compatible = "syscon", "simple-mfd";
234 reg = <0 0x10006000 0 0x1000>;
235
236 spm: power-controller {
237 compatible = "mediatek,mt8173-power-controller";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 #power-domain-cells = <1>;
241
242 /* power domains of the SoC */
243 power-domain@MT8173_POWER_DOMAIN_VDEC {
244 reg = <MT8173_POWER_DOMAIN_VDEC>;
245 clocks = <&topckgen CLK_TOP_MM_SEL>;
246 clock-names = "mm";
247 #power-domain-cells = <0>;
248 };
249 power-domain@MT8173_POWER_DOMAIN_VENC {
250 reg = <MT8173_POWER_DOMAIN_VENC>;
251 clocks = <&topckgen CLK_TOP_MM_SEL>,
252 <&topckgen CLK_TOP_VENC_SEL>;
253 clock-names = "mm", "venc";
254 #power-domain-cells = <0>;
255 };
256 power-domain@MT8173_POWER_DOMAIN_ISP {
257 reg = <MT8173_POWER_DOMAIN_ISP>;
258 clocks = <&topckgen CLK_TOP_MM_SEL>;
259 clock-names = "mm";
260 #power-domain-cells = <0>;
261 };
262 power-domain@MT8173_POWER_DOMAIN_MM {
263 reg = <MT8173_POWER_DOMAIN_MM>;
264 clocks = <&topckgen CLK_TOP_MM_SEL>;
265 clock-names = "mm";
266 #power-domain-cells = <0>;
267 mediatek,infracfg = <&infracfg>;
268 };
269 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
270 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
271 clocks = <&topckgen CLK_TOP_MM_SEL>,
272 <&topckgen CLK_TOP_VENC_LT_SEL>;
273 clock-names = "mm", "venclt";
274 #power-domain-cells = <0>;
275 };
276 power-domain@MT8173_POWER_DOMAIN_AUDIO {
277 reg = <MT8173_POWER_DOMAIN_AUDIO>;
278 #power-domain-cells = <0>;
279 };
280 power-domain@MT8173_POWER_DOMAIN_USB {
281 reg = <MT8173_POWER_DOMAIN_USB>;
282 #power-domain-cells = <0>;
283 };
284 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
285 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
286 clocks = <&clk26m>;
287 clock-names = "mfg";
288 #address-cells = <1>;
289 #size-cells = <0>;
290 #power-domain-cells = <1>;
291
292 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
293 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 #power-domain-cells = <1>;
297
298 power-domain@MT8173_POWER_DOMAIN_MFG {
299 reg = <MT8173_POWER_DOMAIN_MFG>;
300 #power-domain-cells = <0>;
301 mediatek,infracfg = <&infracfg>;
302 };
303 };
304 };
305 };
306 };
307 };