tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display postmask
8
9maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14 Mediatek display postmask, namely POSTMASK, provides round corner pattern
15 generation.
16 POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19 for details.
20
21properties:
22 compatible:
23 oneOf:
24 - items:
25 - const: mediatek,mt8192-disp-postmask
26
27 reg:
28 maxItems: 1
29
30 interrupts:
31 maxItems: 1
32
33 power-domains:
34 description: A phandle and PM domain specifier as defined by bindings of
35 the power controller specified by phandle. See
36 Documentation/devicetree/bindings/power/power-domain.yaml for details.
37
38 clocks:
39 items:
40 - description: POSTMASK Clock
41
42 mediatek,gce-client-reg:
43 description: The register of client driver can be configured by gce with
44 4 arguments defined in this property, such as phandle of gce, subsys id,
45 register offset and size. Each GCE subsys id is mapping to a client
46 defined in the header include/dt-bindings/gce/<chip>-gce.h.
47 $ref: /schemas/types.yaml#/definitions/phandle-array
48 maxItems: 1
49
50required:
51 - compatible
52 - reg
53 - interrupts
54 - power-domains
55 - clocks
56
57additionalProperties: false
58
59examples:
60 - |
61 #include <dt-bindings/interrupt-controller/arm-gic.h>
62 #include <dt-bindings/clock/mt8192-clk.h>
63 #include <dt-bindings/power/mt8192-power.h>
64 #include <dt-bindings/gce/mt8192-gce.h>
65
66 soc {
67 #address-cells = <2>;
68 #size-cells = <2>;
69
70 postmask0: postmask@1400d000 {
71 compatible = "mediatek,mt8192-disp-postmask";
72 reg = <0 0x1400d000 0 0x1000>;
73 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
74 power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
75 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
76 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
77 };
78 };