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Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2021 Linaro Ltd.
5 */
6
7#include <linux/log2.h>
8
9#include "gsi.h"
10#include "ipa_data.h"
11#include "ipa_endpoint.h"
12#include "ipa_mem.h"
13
14/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */
15enum ipa_resource_type {
16 /* Source resource types; first must have value 0 */
17 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
18 IPA_RESOURCE_TYPE_SRC_HDR_SECTORS,
19 IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER,
20 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
21 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
22 IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS,
23 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
24 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
25
26 /* Destination resource types; first must have value 0 */
27 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
28 IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS,
29 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
30};
31
32/* Resource groups used for an SoC having IPA v3.1 */
33enum ipa_rsrc_group_id {
34 /* Source resource group identifiers */
35 IPA_RSRC_GROUP_SRC_UL = 0,
36 IPA_RSRC_GROUP_SRC_DL,
37 IPA_RSRC_GROUP_SRC_DIAG,
38 IPA_RSRC_GROUP_SRC_DMA,
39 IPA_RSRC_GROUP_SRC_UNUSED,
40 IPA_RSRC_GROUP_SRC_UC_RX_Q,
41 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
42
43 /* Destination resource group identifiers */
44 IPA_RSRC_GROUP_DST_UL = 0,
45 IPA_RSRC_GROUP_DST_DL,
46 IPA_RSRC_GROUP_DST_DIAG_DPL,
47 IPA_RSRC_GROUP_DST_DMA,
48 IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL,
49 IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE,
50 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
51};
52
53/* QSB configuration data for an SoC having IPA v3.1 */
54static const struct ipa_qsb_data ipa_qsb_data[] = {
55 [IPA_QSB_MASTER_DDR] = {
56 .max_writes = 8,
57 .max_reads = 8,
58 },
59 [IPA_QSB_MASTER_PCIE] = {
60 .max_writes = 2,
61 .max_reads = 8,
62 },
63};
64
65/* Endpoint data for an SoC having IPA v3.1 */
66static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
67 [IPA_ENDPOINT_AP_COMMAND_TX] = {
68 .ee_id = GSI_EE_AP,
69 .channel_id = 6,
70 .endpoint_id = 22,
71 .toward_ipa = true,
72 .channel = {
73 .tre_count = 256,
74 .event_count = 256,
75 .tlv_count = 18,
76 },
77 .endpoint = {
78 .config = {
79 .resource_group = IPA_RSRC_GROUP_SRC_UL,
80 .dma_mode = true,
81 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
82 .tx = {
83 .seq_type = IPA_SEQ_DMA,
84 },
85 },
86 },
87 },
88 [IPA_ENDPOINT_AP_LAN_RX] = {
89 .ee_id = GSI_EE_AP,
90 .channel_id = 7,
91 .endpoint_id = 15,
92 .toward_ipa = false,
93 .channel = {
94 .tre_count = 256,
95 .event_count = 256,
96 .tlv_count = 8,
97 },
98 .endpoint = {
99 .config = {
100 .resource_group = IPA_RSRC_GROUP_SRC_UL,
101 .aggregation = true,
102 .status_enable = true,
103 .rx = {
104 .buffer_size = 8192,
105 .pad_align = ilog2(sizeof(u32)),
106 },
107 },
108 },
109 },
110 [IPA_ENDPOINT_AP_MODEM_TX] = {
111 .ee_id = GSI_EE_AP,
112 .channel_id = 5,
113 .endpoint_id = 3,
114 .toward_ipa = true,
115 .channel = {
116 .tre_count = 512,
117 .event_count = 512,
118 .tlv_count = 16,
119 },
120 .endpoint = {
121 .filter_support = true,
122 .config = {
123 .resource_group = IPA_RSRC_GROUP_SRC_UL,
124 .checksum = true,
125 .qmap = true,
126 .status_enable = true,
127 .tx = {
128 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
129 .status_endpoint =
130 IPA_ENDPOINT_MODEM_AP_RX,
131 },
132 },
133 },
134 },
135 [IPA_ENDPOINT_AP_MODEM_RX] = {
136 .ee_id = GSI_EE_AP,
137 .channel_id = 8,
138 .endpoint_id = 16,
139 .toward_ipa = false,
140 .channel = {
141 .tre_count = 256,
142 .event_count = 256,
143 .tlv_count = 8,
144 },
145 .endpoint = {
146 .config = {
147 .resource_group = IPA_RSRC_GROUP_DST_DL,
148 .checksum = true,
149 .qmap = true,
150 .aggregation = true,
151 .rx = {
152 .buffer_size = 8192,
153 .aggr_close_eof = true,
154 },
155 },
156 },
157 },
158 [IPA_ENDPOINT_MODEM_LAN_TX] = {
159 .ee_id = GSI_EE_MODEM,
160 .channel_id = 4,
161 .endpoint_id = 9,
162 .toward_ipa = true,
163 .endpoint = {
164 .filter_support = true,
165 },
166 },
167 [IPA_ENDPOINT_MODEM_AP_TX] = {
168 .ee_id = GSI_EE_MODEM,
169 .channel_id = 0,
170 .endpoint_id = 5,
171 .toward_ipa = true,
172 .endpoint = {
173 .filter_support = true,
174 },
175 },
176 [IPA_ENDPOINT_MODEM_AP_RX] = {
177 .ee_id = GSI_EE_MODEM,
178 .channel_id = 5,
179 .endpoint_id = 18,
180 .toward_ipa = false,
181 },
182};
183
184/* Source resource configuration data for an SoC having IPA v3.1 */
185static const struct ipa_resource ipa_resource_src[] = {
186 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
187 .limits[IPA_RSRC_GROUP_SRC_UL] = {
188 .min = 3, .max = 255,
189 },
190 .limits[IPA_RSRC_GROUP_SRC_DL] = {
191 .min = 3, .max = 255,
192 },
193 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
194 .min = 1, .max = 255,
195 },
196 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
197 .min = 1, .max = 255,
198 },
199 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
200 .min = 2, .max = 255,
201 },
202 },
203 [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = {
204 .limits[IPA_RSRC_GROUP_SRC_UL] = {
205 .min = 0, .max = 255,
206 },
207 .limits[IPA_RSRC_GROUP_SRC_DL] = {
208 .min = 0, .max = 255,
209 },
210 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
211 .min = 0, .max = 255,
212 },
213 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
214 .min = 0, .max = 255,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
217 .min = 0, .max = 255,
218 },
219 },
220 [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = {
221 .limits[IPA_RSRC_GROUP_SRC_UL] = {
222 .min = 0, .max = 255,
223 },
224 .limits[IPA_RSRC_GROUP_SRC_DL] = {
225 .min = 0, .max = 255,
226 },
227 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
228 .min = 0, .max = 255,
229 },
230 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
231 .min = 0, .max = 255,
232 },
233 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
234 .min = 0, .max = 255,
235 },
236 },
237 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
238 .limits[IPA_RSRC_GROUP_SRC_UL] = {
239 .min = 14, .max = 14,
240 },
241 .limits[IPA_RSRC_GROUP_SRC_DL] = {
242 .min = 16, .max = 16,
243 },
244 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
245 .min = 5, .max = 5,
246 },
247 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
248 .min = 5, .max = 5,
249 },
250 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
251 .min = 8, .max = 8,
252 },
253 },
254 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
255 .limits[IPA_RSRC_GROUP_SRC_UL] = {
256 .min = 19, .max = 19,
257 },
258 .limits[IPA_RSRC_GROUP_SRC_DL] = {
259 .min = 26, .max = 26,
260 },
261 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
262 .min = 5, .max = 5, /* 3 downstream */
263 },
264 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
265 .min = 5, .max = 5, /* 7 downstream */
266 },
267 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
268 .min = 8, .max = 8,
269 },
270 },
271 [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = {
272 .limits[IPA_RSRC_GROUP_SRC_UL] = {
273 .min = 0, .max = 255,
274 },
275 .limits[IPA_RSRC_GROUP_SRC_DL] = {
276 .min = 0, .max = 255,
277 },
278 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
279 .min = 0, .max = 255,
280 },
281 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
282 .min = 0, .max = 255,
283 },
284 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
285 .min = 0, .max = 255,
286 },
287 },
288 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
289 .limits[IPA_RSRC_GROUP_SRC_UL] = {
290 .min = 0, .max = 255,
291 },
292 .limits[IPA_RSRC_GROUP_SRC_DL] = {
293 .min = 0, .max = 255,
294 },
295 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
296 .min = 0, .max = 255,
297 },
298 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
299 .min = 0, .max = 255,
300 },
301 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
302 .min = 0, .max = 255,
303 },
304 },
305 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
306 .limits[IPA_RSRC_GROUP_SRC_UL] = {
307 .min = 19, .max = 19,
308 },
309 .limits[IPA_RSRC_GROUP_SRC_DL] = {
310 .min = 26, .max = 26,
311 },
312 .limits[IPA_RSRC_GROUP_SRC_DIAG] = {
313 .min = 5, .max = 5,
314 },
315 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
316 .min = 5, .max = 5,
317 },
318 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
319 .min = 8, .max = 8,
320 },
321 },
322};
323
324/* Destination resource configuration data for an SoC having IPA v3.1 */
325static const struct ipa_resource ipa_resource_dst[] = {
326 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
327 .limits[IPA_RSRC_GROUP_DST_UL] = {
328 .min = 3, .max = 3, /* 2 downstream */
329 },
330 .limits[IPA_RSRC_GROUP_DST_DL] = {
331 .min = 3, .max = 3,
332 },
333 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
334 .min = 1, .max = 1, /* 0 downstream */
335 },
336 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
337 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
338 .min = 3, .max = 3,
339 },
340 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
341 .min = 3, .max = 3,
342 },
343 },
344 [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = {
345 .limits[IPA_RSRC_GROUP_DST_UL] = {
346 .min = 0, .max = 255,
347 },
348 .limits[IPA_RSRC_GROUP_DST_DL] = {
349 .min = 0, .max = 255,
350 },
351 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
352 .min = 0, .max = 255,
353 },
354 .limits[IPA_RSRC_GROUP_DST_DMA] = {
355 .min = 0, .max = 255,
356 },
357 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
358 .min = 0, .max = 255,
359 },
360 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = {
361 .min = 0, .max = 255,
362 },
363 },
364 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
365 .limits[IPA_RSRC_GROUP_DST_UL] = {
366 .min = 1, .max = 1,
367 },
368 .limits[IPA_RSRC_GROUP_DST_DL] = {
369 .min = 1, .max = 1,
370 },
371 .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = {
372 .min = 1, .max = 1,
373 },
374 .limits[IPA_RSRC_GROUP_DST_DMA] = {
375 .min = 1, .max = 1,
376 },
377 .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = {
378 .min = 1, .max = 1,
379 },
380 },
381};
382
383/* Resource configuration data for an SoC having IPA v3.1 */
384static const struct ipa_resource_data ipa_resource_data = {
385 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
386 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
387 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
388 .resource_src = ipa_resource_src,
389 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
390 .resource_dst = ipa_resource_dst,
391};
392
393/* IPA-resident memory region data for an SoC having IPA v3.1 */
394static const struct ipa_mem ipa_mem_local_data[] = {
395 {
396 .id = IPA_MEM_UC_SHARED,
397 .offset = 0x0000,
398 .size = 0x0080,
399 .canary_count = 0,
400 },
401 {
402 .id = IPA_MEM_UC_INFO,
403 .offset = 0x0080,
404 .size = 0x0200,
405 .canary_count = 0,
406 },
407 {
408 .id = IPA_MEM_V4_FILTER_HASHED,
409 .offset = 0x0288,
410 .size = 0x0078,
411 .canary_count = 2,
412 },
413 {
414 .id = IPA_MEM_V4_FILTER,
415 .offset = 0x0308,
416 .size = 0x0078,
417 .canary_count = 2,
418 },
419 {
420 .id = IPA_MEM_V6_FILTER_HASHED,
421 .offset = 0x0388,
422 .size = 0x0078,
423 .canary_count = 2,
424 },
425 {
426 .id = IPA_MEM_V6_FILTER,
427 .offset = 0x0408,
428 .size = 0x0078,
429 .canary_count = 2,
430 },
431 {
432 .id = IPA_MEM_V4_ROUTE_HASHED,
433 .offset = 0x0488,
434 .size = 0x0078,
435 .canary_count = 2,
436 },
437 {
438 .id = IPA_MEM_V4_ROUTE,
439 .offset = 0x0508,
440 .size = 0x0078,
441 .canary_count = 2,
442 },
443 {
444 .id = IPA_MEM_V6_ROUTE_HASHED,
445 .offset = 0x0588,
446 .size = 0x0078,
447 .canary_count = 2,
448 },
449 {
450 .id = IPA_MEM_V6_ROUTE,
451 .offset = 0x0608,
452 .size = 0x0078,
453 .canary_count = 2,
454 },
455 {
456 .id = IPA_MEM_MODEM_HEADER,
457 .offset = 0x0688,
458 .size = 0x0140,
459 .canary_count = 2,
460 },
461 {
462 .id = IPA_MEM_MODEM_PROC_CTX,
463 .offset = 0x07d0,
464 .size = 0x0200,
465 .canary_count = 2,
466 },
467 {
468 .id = IPA_MEM_AP_PROC_CTX,
469 .offset = 0x09d0,
470 .size = 0x0200,
471 .canary_count = 0,
472 },
473 {
474 .id = IPA_MEM_MODEM,
475 .offset = 0x0bd8,
476 .size = 0x1424,
477 .canary_count = 0,
478 },
479 {
480 .id = IPA_MEM_END_MARKER,
481 .offset = 0x2000,
482 .size = 0,
483 .canary_count = 1,
484 },
485};
486
487/* Memory configuration data for an SoC having IPA v3.1 */
488static const struct ipa_mem_data ipa_mem_data = {
489 .local_count = ARRAY_SIZE(ipa_mem_local_data),
490 .local = ipa_mem_local_data,
491 .imem_addr = 0x146bd000,
492 .imem_size = 0x00002000,
493 .smem_id = 497,
494 .smem_size = 0x00002000,
495};
496
497/* Interconnect bandwidths are in 1000 byte/second units */
498static const struct ipa_interconnect_data ipa_interconnect_data[] = {
499 {
500 .name = "memory",
501 .peak_bandwidth = 640000, /* 640 MBps */
502 .average_bandwidth = 80000, /* 80 MBps */
503 },
504 {
505 .name = "imem",
506 .peak_bandwidth = 640000, /* 640 MBps */
507 .average_bandwidth = 80000, /* 80 MBps */
508 },
509 /* Average bandwidth is unused for the next interconnect */
510 {
511 .name = "config",
512 .peak_bandwidth = 80000, /* 80 MBps */
513 .average_bandwidth = 0, /* unused */
514 },
515};
516
517/* Clock and interconnect configuration data for an SoC having IPA v3.1 */
518static const struct ipa_power_data ipa_power_data = {
519 .core_clock_rate = 16 * 1000 * 1000, /* Hz */
520 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
521 .interconnect_data = ipa_interconnect_data,
522};
523
524/* Configuration data for an SoC having IPA v3.1 */
525const struct ipa_data ipa_data_v3_1 = {
526 .version = IPA_VERSION_3_1,
527 .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK,
528 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
529 .qsb_data = ipa_qsb_data,
530 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
531 .endpoint_data = ipa_gsi_endpoint_data,
532 .resource_data = &ipa_resource_data,
533 .mem_data = &ipa_mem_data,
534 .power_data = &ipa_power_data,
535};