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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
4#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
5
6#include "mtk-pm-domains.h"
7#include <dt-bindings/power/mt8192-power.h>
8
9/*
10 * MT8192 power domain support
11 */
12
13static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
14 [MT8192_POWER_DOMAIN_AUDIO] = {
15 .name = "audio",
16 .sta_mask = BIT(21),
17 .ctl_offs = 0x0354,
18 .pwr_sta_offs = 0x016c,
19 .pwr_sta2nd_offs = 0x0170,
20 .sram_pdn_bits = GENMASK(8, 8),
21 .sram_pdn_ack_bits = GENMASK(12, 12),
22 .bp_infracfg = {
23 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
24 MT8192_TOP_AXI_PROT_EN_2_SET,
25 MT8192_TOP_AXI_PROT_EN_2_CLR,
26 MT8192_TOP_AXI_PROT_EN_2_STA1),
27 },
28 },
29 [MT8192_POWER_DOMAIN_CONN] = {
30 .name = "conn",
31 .sta_mask = PWR_STATUS_CONN,
32 .ctl_offs = 0x0304,
33 .pwr_sta_offs = 0x016c,
34 .pwr_sta2nd_offs = 0x0170,
35 .sram_pdn_bits = 0,
36 .sram_pdn_ack_bits = 0,
37 .bp_infracfg = {
38 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
39 MT8192_TOP_AXI_PROT_EN_SET,
40 MT8192_TOP_AXI_PROT_EN_CLR,
41 MT8192_TOP_AXI_PROT_EN_STA1),
42 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
43 MT8192_TOP_AXI_PROT_EN_SET,
44 MT8192_TOP_AXI_PROT_EN_CLR,
45 MT8192_TOP_AXI_PROT_EN_STA1),
46 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
47 MT8192_TOP_AXI_PROT_EN_1_SET,
48 MT8192_TOP_AXI_PROT_EN_1_CLR,
49 MT8192_TOP_AXI_PROT_EN_1_STA1),
50 },
51 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
52 },
53 [MT8192_POWER_DOMAIN_MFG0] = {
54 .name = "mfg0",
55 .sta_mask = BIT(2),
56 .ctl_offs = 0x0308,
57 .pwr_sta_offs = 0x016c,
58 .pwr_sta2nd_offs = 0x0170,
59 .sram_pdn_bits = GENMASK(8, 8),
60 .sram_pdn_ack_bits = GENMASK(12, 12),
61 },
62 [MT8192_POWER_DOMAIN_MFG1] = {
63 .name = "mfg1",
64 .sta_mask = BIT(3),
65 .ctl_offs = 0x030c,
66 .pwr_sta_offs = 0x016c,
67 .pwr_sta2nd_offs = 0x0170,
68 .sram_pdn_bits = GENMASK(8, 8),
69 .sram_pdn_ack_bits = GENMASK(12, 12),
70 .bp_infracfg = {
71 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
72 MT8192_TOP_AXI_PROT_EN_1_SET,
73 MT8192_TOP_AXI_PROT_EN_1_CLR,
74 MT8192_TOP_AXI_PROT_EN_1_STA1),
75 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
76 MT8192_TOP_AXI_PROT_EN_2_SET,
77 MT8192_TOP_AXI_PROT_EN_2_CLR,
78 MT8192_TOP_AXI_PROT_EN_2_STA1),
79 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
80 MT8192_TOP_AXI_PROT_EN_SET,
81 MT8192_TOP_AXI_PROT_EN_CLR,
82 MT8192_TOP_AXI_PROT_EN_STA1),
83 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
84 MT8192_TOP_AXI_PROT_EN_2_SET,
85 MT8192_TOP_AXI_PROT_EN_2_CLR,
86 MT8192_TOP_AXI_PROT_EN_2_STA1),
87 },
88 },
89 [MT8192_POWER_DOMAIN_MFG2] = {
90 .name = "mfg2",
91 .sta_mask = BIT(4),
92 .ctl_offs = 0x0310,
93 .pwr_sta_offs = 0x016c,
94 .pwr_sta2nd_offs = 0x0170,
95 .sram_pdn_bits = GENMASK(8, 8),
96 .sram_pdn_ack_bits = GENMASK(12, 12),
97 },
98 [MT8192_POWER_DOMAIN_MFG3] = {
99 .name = "mfg3",
100 .sta_mask = BIT(5),
101 .ctl_offs = 0x0314,
102 .pwr_sta_offs = 0x016c,
103 .pwr_sta2nd_offs = 0x0170,
104 .sram_pdn_bits = GENMASK(8, 8),
105 .sram_pdn_ack_bits = GENMASK(12, 12),
106 },
107 [MT8192_POWER_DOMAIN_MFG4] = {
108 .name = "mfg4",
109 .sta_mask = BIT(6),
110 .ctl_offs = 0x0318,
111 .pwr_sta_offs = 0x016c,
112 .pwr_sta2nd_offs = 0x0170,
113 .sram_pdn_bits = GENMASK(8, 8),
114 .sram_pdn_ack_bits = GENMASK(12, 12),
115 },
116 [MT8192_POWER_DOMAIN_MFG5] = {
117 .name = "mfg5",
118 .sta_mask = BIT(7),
119 .ctl_offs = 0x031c,
120 .pwr_sta_offs = 0x016c,
121 .pwr_sta2nd_offs = 0x0170,
122 .sram_pdn_bits = GENMASK(8, 8),
123 .sram_pdn_ack_bits = GENMASK(12, 12),
124 },
125 [MT8192_POWER_DOMAIN_MFG6] = {
126 .name = "mfg6",
127 .sta_mask = BIT(8),
128 .ctl_offs = 0x0320,
129 .pwr_sta_offs = 0x016c,
130 .pwr_sta2nd_offs = 0x0170,
131 .sram_pdn_bits = GENMASK(8, 8),
132 .sram_pdn_ack_bits = GENMASK(12, 12),
133 },
134 [MT8192_POWER_DOMAIN_DISP] = {
135 .name = "disp",
136 .sta_mask = BIT(20),
137 .ctl_offs = 0x0350,
138 .pwr_sta_offs = 0x016c,
139 .pwr_sta2nd_offs = 0x0170,
140 .sram_pdn_bits = GENMASK(8, 8),
141 .sram_pdn_ack_bits = GENMASK(12, 12),
142 .bp_infracfg = {
143 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
144 MT8192_TOP_AXI_PROT_EN_MM_SET,
145 MT8192_TOP_AXI_PROT_EN_MM_CLR,
146 MT8192_TOP_AXI_PROT_EN_MM_STA1),
147 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
148 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
149 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
150 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
151 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
152 MT8192_TOP_AXI_PROT_EN_SET,
153 MT8192_TOP_AXI_PROT_EN_CLR,
154 MT8192_TOP_AXI_PROT_EN_STA1),
155 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
156 MT8192_TOP_AXI_PROT_EN_MM_SET,
157 MT8192_TOP_AXI_PROT_EN_MM_CLR,
158 MT8192_TOP_AXI_PROT_EN_MM_STA1),
159 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
160 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
161 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
162 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
163 },
164 },
165 [MT8192_POWER_DOMAIN_IPE] = {
166 .name = "ipe",
167 .sta_mask = BIT(14),
168 .ctl_offs = 0x0338,
169 .pwr_sta_offs = 0x016c,
170 .pwr_sta2nd_offs = 0x0170,
171 .sram_pdn_bits = GENMASK(8, 8),
172 .sram_pdn_ack_bits = GENMASK(12, 12),
173 .bp_infracfg = {
174 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
175 MT8192_TOP_AXI_PROT_EN_MM_SET,
176 MT8192_TOP_AXI_PROT_EN_MM_CLR,
177 MT8192_TOP_AXI_PROT_EN_MM_STA1),
178 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
179 MT8192_TOP_AXI_PROT_EN_MM_SET,
180 MT8192_TOP_AXI_PROT_EN_MM_CLR,
181 MT8192_TOP_AXI_PROT_EN_MM_STA1),
182 },
183 },
184 [MT8192_POWER_DOMAIN_ISP] = {
185 .name = "isp",
186 .sta_mask = BIT(12),
187 .ctl_offs = 0x0330,
188 .pwr_sta_offs = 0x016c,
189 .pwr_sta2nd_offs = 0x0170,
190 .sram_pdn_bits = GENMASK(8, 8),
191 .sram_pdn_ack_bits = GENMASK(12, 12),
192 .bp_infracfg = {
193 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
194 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
195 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
196 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
197 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
198 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
199 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
200 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
201 },
202 },
203 [MT8192_POWER_DOMAIN_ISP2] = {
204 .name = "isp2",
205 .sta_mask = BIT(13),
206 .ctl_offs = 0x0334,
207 .pwr_sta_offs = 0x016c,
208 .pwr_sta2nd_offs = 0x0170,
209 .sram_pdn_bits = GENMASK(8, 8),
210 .sram_pdn_ack_bits = GENMASK(12, 12),
211 .bp_infracfg = {
212 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
213 MT8192_TOP_AXI_PROT_EN_MM_SET,
214 MT8192_TOP_AXI_PROT_EN_MM_CLR,
215 MT8192_TOP_AXI_PROT_EN_MM_STA1),
216 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
217 MT8192_TOP_AXI_PROT_EN_MM_SET,
218 MT8192_TOP_AXI_PROT_EN_MM_CLR,
219 MT8192_TOP_AXI_PROT_EN_MM_STA1),
220 },
221 },
222 [MT8192_POWER_DOMAIN_MDP] = {
223 .name = "mdp",
224 .sta_mask = BIT(19),
225 .ctl_offs = 0x034c,
226 .pwr_sta_offs = 0x016c,
227 .pwr_sta2nd_offs = 0x0170,
228 .sram_pdn_bits = GENMASK(8, 8),
229 .sram_pdn_ack_bits = GENMASK(12, 12),
230 .bp_infracfg = {
231 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
232 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
233 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
234 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
235 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
236 MT8192_TOP_AXI_PROT_EN_MM_2_SET,
237 MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
238 MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
239 },
240 },
241 [MT8192_POWER_DOMAIN_VENC] = {
242 .name = "venc",
243 .sta_mask = BIT(17),
244 .ctl_offs = 0x0344,
245 .pwr_sta_offs = 0x016c,
246 .pwr_sta2nd_offs = 0x0170,
247 .sram_pdn_bits = GENMASK(8, 8),
248 .sram_pdn_ack_bits = GENMASK(12, 12),
249 .bp_infracfg = {
250 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
251 MT8192_TOP_AXI_PROT_EN_MM_SET,
252 MT8192_TOP_AXI_PROT_EN_MM_CLR,
253 MT8192_TOP_AXI_PROT_EN_MM_STA1),
254 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
255 MT8192_TOP_AXI_PROT_EN_MM_SET,
256 MT8192_TOP_AXI_PROT_EN_MM_CLR,
257 MT8192_TOP_AXI_PROT_EN_MM_STA1),
258 },
259 },
260 [MT8192_POWER_DOMAIN_VDEC] = {
261 .name = "vdec",
262 .sta_mask = BIT(15),
263 .ctl_offs = 0x033c,
264 .pwr_sta_offs = 0x016c,
265 .pwr_sta2nd_offs = 0x0170,
266 .sram_pdn_bits = GENMASK(8, 8),
267 .sram_pdn_ack_bits = GENMASK(12, 12),
268 .bp_infracfg = {
269 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
270 MT8192_TOP_AXI_PROT_EN_MM_SET,
271 MT8192_TOP_AXI_PROT_EN_MM_CLR,
272 MT8192_TOP_AXI_PROT_EN_MM_STA1),
273 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
274 MT8192_TOP_AXI_PROT_EN_MM_SET,
275 MT8192_TOP_AXI_PROT_EN_MM_CLR,
276 MT8192_TOP_AXI_PROT_EN_MM_STA1),
277 },
278 },
279 [MT8192_POWER_DOMAIN_VDEC2] = {
280 .name = "vdec2",
281 .sta_mask = BIT(16),
282 .ctl_offs = 0x0340,
283 .pwr_sta_offs = 0x016c,
284 .pwr_sta2nd_offs = 0x0170,
285 .sram_pdn_bits = GENMASK(8, 8),
286 .sram_pdn_ack_bits = GENMASK(12, 12),
287 },
288 [MT8192_POWER_DOMAIN_CAM] = {
289 .name = "cam",
290 .sta_mask = BIT(23),
291 .ctl_offs = 0x035c,
292 .pwr_sta_offs = 0x016c,
293 .pwr_sta2nd_offs = 0x0170,
294 .sram_pdn_bits = GENMASK(8, 8),
295 .sram_pdn_ack_bits = GENMASK(12, 12),
296 .bp_infracfg = {
297 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
298 MT8192_TOP_AXI_PROT_EN_2_SET,
299 MT8192_TOP_AXI_PROT_EN_2_CLR,
300 MT8192_TOP_AXI_PROT_EN_2_STA1),
301 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
302 MT8192_TOP_AXI_PROT_EN_MM_SET,
303 MT8192_TOP_AXI_PROT_EN_MM_CLR,
304 MT8192_TOP_AXI_PROT_EN_MM_STA1),
305 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
306 MT8192_TOP_AXI_PROT_EN_1_SET,
307 MT8192_TOP_AXI_PROT_EN_1_CLR,
308 MT8192_TOP_AXI_PROT_EN_1_STA1),
309 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
310 MT8192_TOP_AXI_PROT_EN_MM_SET,
311 MT8192_TOP_AXI_PROT_EN_MM_CLR,
312 MT8192_TOP_AXI_PROT_EN_MM_STA1),
313 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
314 MT8192_TOP_AXI_PROT_EN_VDNR_SET,
315 MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
316 MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
317 },
318 },
319 [MT8192_POWER_DOMAIN_CAM_RAWA] = {
320 .name = "cam_rawa",
321 .sta_mask = BIT(24),
322 .ctl_offs = 0x0360,
323 .pwr_sta_offs = 0x016c,
324 .pwr_sta2nd_offs = 0x0170,
325 .sram_pdn_bits = GENMASK(8, 8),
326 .sram_pdn_ack_bits = GENMASK(12, 12),
327 },
328 [MT8192_POWER_DOMAIN_CAM_RAWB] = {
329 .name = "cam_rawb",
330 .sta_mask = BIT(25),
331 .ctl_offs = 0x0364,
332 .pwr_sta_offs = 0x016c,
333 .pwr_sta2nd_offs = 0x0170,
334 .sram_pdn_bits = GENMASK(8, 8),
335 .sram_pdn_ack_bits = GENMASK(12, 12),
336 },
337 [MT8192_POWER_DOMAIN_CAM_RAWC] = {
338 .name = "cam_rawc",
339 .sta_mask = BIT(26),
340 .ctl_offs = 0x0368,
341 .pwr_sta_offs = 0x016c,
342 .pwr_sta2nd_offs = 0x0170,
343 .sram_pdn_bits = GENMASK(8, 8),
344 .sram_pdn_ack_bits = GENMASK(12, 12),
345 },
346};
347
348static const struct scpsys_soc_data mt8192_scpsys_data = {
349 .domains_data = scpsys_domain_data_mt8192,
350 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
351};
352
353#endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */