tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device access for Crystal Cove PMIC
4 *
5 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
6 *
7 * Author: Yang, Bin <bin.yang@intel.com>
8 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
9 */
10
11#include <linux/interrupt.h>
12#include <linux/regmap.h>
13#include <linux/mfd/core.h>
14#include <linux/mfd/intel_soc_pmic.h>
15
16#include "intel_soc_pmic_core.h"
17
18#define CRYSTAL_COVE_MAX_REGISTER 0xC6
19
20#define CRYSTAL_COVE_REG_IRQLVL1 0x02
21#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
22
23#define CRYSTAL_COVE_IRQ_PWRSRC 0
24#define CRYSTAL_COVE_IRQ_THRM 1
25#define CRYSTAL_COVE_IRQ_BCU 2
26#define CRYSTAL_COVE_IRQ_ADC 3
27#define CRYSTAL_COVE_IRQ_CHGR 4
28#define CRYSTAL_COVE_IRQ_GPIO 5
29#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
30
31static const struct resource pwrsrc_resources[] = {
32 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
33};
34
35static const struct resource thermal_resources[] = {
36 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
37};
38
39static const struct resource bcu_resources[] = {
40 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
41};
42
43static const struct resource adc_resources[] = {
44 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
45};
46
47static const struct resource charger_resources[] = {
48 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
49};
50
51static const struct resource gpio_resources[] = {
52 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
53};
54
55static struct mfd_cell crystal_cove_byt_dev[] = {
56 {
57 .name = "crystal_cove_pwrsrc",
58 .num_resources = ARRAY_SIZE(pwrsrc_resources),
59 .resources = pwrsrc_resources,
60 },
61 {
62 .name = "crystal_cove_thermal",
63 .num_resources = ARRAY_SIZE(thermal_resources),
64 .resources = thermal_resources,
65 },
66 {
67 .name = "crystal_cove_bcu",
68 .num_resources = ARRAY_SIZE(bcu_resources),
69 .resources = bcu_resources,
70 },
71 {
72 .name = "crystal_cove_adc",
73 .num_resources = ARRAY_SIZE(adc_resources),
74 .resources = adc_resources,
75 },
76 {
77 .name = "crystal_cove_charger",
78 .num_resources = ARRAY_SIZE(charger_resources),
79 .resources = charger_resources,
80 },
81 {
82 .name = "crystal_cove_gpio",
83 .num_resources = ARRAY_SIZE(gpio_resources),
84 .resources = gpio_resources,
85 },
86 {
87 .name = "byt_crystal_cove_pmic",
88 },
89 {
90 .name = "crystal_cove_pwm",
91 },
92};
93
94static struct mfd_cell crystal_cove_cht_dev[] = {
95 {
96 .name = "crystal_cove_gpio",
97 .num_resources = ARRAY_SIZE(gpio_resources),
98 .resources = gpio_resources,
99 },
100 {
101 .name = "cht_crystal_cove_pmic",
102 },
103 {
104 .name = "crystal_cove_pwm",
105 },
106};
107
108static const struct regmap_config crystal_cove_regmap_config = {
109 .reg_bits = 8,
110 .val_bits = 8,
111
112 .max_register = CRYSTAL_COVE_MAX_REGISTER,
113 .cache_type = REGCACHE_NONE,
114};
115
116static const struct regmap_irq crystal_cove_irqs[] = {
117 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
118 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
119 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
120 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
121 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
122 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
123 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
124};
125
126static const struct regmap_irq_chip crystal_cove_irq_chip = {
127 .name = "Crystal Cove",
128 .irqs = crystal_cove_irqs,
129 .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
130 .num_regs = 1,
131 .status_base = CRYSTAL_COVE_REG_IRQLVL1,
132 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
133};
134
135struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
136 .irq_flags = IRQF_TRIGGER_RISING,
137 .cell_dev = crystal_cove_byt_dev,
138 .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
139 .regmap_config = &crystal_cove_regmap_config,
140 .irq_chip = &crystal_cove_irq_chip,
141};
142
143struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
144 .irq_flags = IRQF_TRIGGER_RISING,
145 .cell_dev = crystal_cove_cht_dev,
146 .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
147 .regmap_config = &crystal_cove_regmap_config,
148 .irq_chip = &crystal_cove_irq_chip,
149};