tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Common Clock Framework support for Exynos850 SoC.
7 */
8
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14
15#include <dt-bindings/clock/exynos850.h>
16
17#include "clk.h"
18#include "clk-exynos-arm64.h"
19
20/* ---- CMU_TOP ------------------------------------------------------------- */
21
22/* Register Offset definitions for CMU_TOP (0x120e0000) */
23#define PLL_LOCKTIME_PLL_MMC 0x0000
24#define PLL_LOCKTIME_PLL_SHARED0 0x0004
25#define PLL_LOCKTIME_PLL_SHARED1 0x0008
26#define PLL_CON0_PLL_MMC 0x0100
27#define PLL_CON3_PLL_MMC 0x010c
28#define PLL_CON0_PLL_SHARED0 0x0140
29#define PLL_CON3_PLL_SHARED0 0x014c
30#define PLL_CON0_PLL_SHARED1 0x0180
31#define PLL_CON3_PLL_SHARED1 0x018c
32#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
33#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
34#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
35#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
36#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
37#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
38#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
39#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
40#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
41#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
42#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
43#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
44#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
45#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
46#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
47#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
48#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
49#define CLK_CON_DIV_CLKCMU_DPU 0x1840
50#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
51#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
52#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
53#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
54#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
55#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
56#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
57#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
58#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
59#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
60#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
61#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
62#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
63#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
64#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
65#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
66#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
67#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
68#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
69#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
70#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
71#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
72#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
73#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
74
75static const unsigned long top_clk_regs[] __initconst = {
76 PLL_LOCKTIME_PLL_MMC,
77 PLL_LOCKTIME_PLL_SHARED0,
78 PLL_LOCKTIME_PLL_SHARED1,
79 PLL_CON0_PLL_MMC,
80 PLL_CON3_PLL_MMC,
81 PLL_CON0_PLL_SHARED0,
82 PLL_CON3_PLL_SHARED0,
83 PLL_CON0_PLL_SHARED1,
84 PLL_CON3_PLL_SHARED1,
85 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
86 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
87 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
88 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
89 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
90 CLK_CON_MUX_MUX_CLKCMU_DPU,
91 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
92 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
93 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
94 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
95 CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
96 CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
97 CLK_CON_DIV_CLKCMU_APM_BUS,
98 CLK_CON_DIV_CLKCMU_CORE_BUS,
99 CLK_CON_DIV_CLKCMU_CORE_CCI,
100 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
101 CLK_CON_DIV_CLKCMU_CORE_SSS,
102 CLK_CON_DIV_CLKCMU_DPU,
103 CLK_CON_DIV_CLKCMU_HSI_BUS,
104 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
105 CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
106 CLK_CON_DIV_CLKCMU_PERI_BUS,
107 CLK_CON_DIV_CLKCMU_PERI_IP,
108 CLK_CON_DIV_CLKCMU_PERI_UART,
109 CLK_CON_DIV_PLL_SHARED0_DIV2,
110 CLK_CON_DIV_PLL_SHARED0_DIV3,
111 CLK_CON_DIV_PLL_SHARED0_DIV4,
112 CLK_CON_DIV_PLL_SHARED1_DIV2,
113 CLK_CON_DIV_PLL_SHARED1_DIV3,
114 CLK_CON_DIV_PLL_SHARED1_DIV4,
115 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
116 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
117 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
118 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
119 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
120 CLK_CON_GAT_GATE_CLKCMU_DPU,
121 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
122 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
123 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
124 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
125 CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
126 CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
127};
128
129/*
130 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
131 * for those PLLs by default, so set_rate operation would fail.
132 */
133static const struct samsung_pll_clock top_pll_clks[] __initconst = {
134 /* CMU_TOP_PURECLKCOMP */
135 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
136 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
137 NULL),
138 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
139 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
140 NULL),
141 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
142 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
143};
144
145/* List of parent clocks for Muxes in CMU_TOP */
146PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
147PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
148PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
149/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
150PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
151/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
152PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
153 "dout_shared1_div3", "dout_shared0_div4" };
154PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
155 "dout_shared0_div3", "dout_shared1_div3" };
156PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
157 "dout_shared1_div2", "dout_shared0_div3",
158 "dout_shared1_div3", "mout_mmc_pll",
159 "oscclk", "oscclk" };
160PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
161 "dout_shared0_div4", "dout_shared1_div4" };
162/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
163PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
164PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
165 "dout_shared1_div2", "dout_shared0_div3",
166 "dout_shared1_div3", "mout_mmc_pll",
167 "oscclk", "oscclk" };
168PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
169 "dout_shared1_div4", "oscclk" };
170/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
171PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
172PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
173 "dout_shared1_div4", "oscclk" };
174PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
175 "dout_shared1_div4", "oscclk" };
176
177/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
178PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
179 "dout_shared0_div4", "dout_shared1_div4" };
180
181static const struct samsung_mux_clock top_mux_clks[] __initconst = {
182 /* CMU_TOP_PURECLKCOMP */
183 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
184 PLL_CON0_PLL_SHARED0, 4, 1),
185 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
186 PLL_CON0_PLL_SHARED1, 4, 1),
187 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
188 PLL_CON0_PLL_MMC, 4, 1),
189
190 /* APM */
191 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
192 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
193
194 /* CORE */
195 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
196 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
197 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
198 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
199 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
200 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
201 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
202 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
203
204 /* DPU */
205 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
206 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
207
208 /* HSI */
209 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
210 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
211 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
212 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
213 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
214 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
215
216 /* PERI */
217 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
218 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
219 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
220 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
221 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
222 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
223};
224
225static const struct samsung_div_clock top_div_clks[] __initconst = {
226 /* CMU_TOP_PURECLKCOMP */
227 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
228 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
229 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
230 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
231 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
232 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
233 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
234 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
235 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
236 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
237 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
238 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
239
240 /* APM */
241 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
242 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
243
244 /* CORE */
245 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
246 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
247 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
248 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
249 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
250 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
251 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
252 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
253
254 /* DPU */
255 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
256 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
257
258 /* HSI */
259 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
260 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
261 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
262 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
263 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
264 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
265
266 /* PERI */
267 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
268 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
269 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
270 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
271 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
272 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
273};
274
275static const struct samsung_gate_clock top_gate_clks[] __initconst = {
276 /* CORE */
277 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
278 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
279 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
280 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
281 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
282 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
283 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
284 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
285
286 /* APM */
287 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
288 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
289
290 /* DPU */
291 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
292 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
293
294 /* HSI */
295 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
296 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
297 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
298 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
299 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
300 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
301
302 /* PERI */
303 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
304 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
305 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
306 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
307 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
308 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
309};
310
311static const struct samsung_cmu_info top_cmu_info __initconst = {
312 .pll_clks = top_pll_clks,
313 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
314 .mux_clks = top_mux_clks,
315 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
316 .div_clks = top_div_clks,
317 .nr_div_clks = ARRAY_SIZE(top_div_clks),
318 .gate_clks = top_gate_clks,
319 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
320 .nr_clk_ids = TOP_NR_CLK,
321 .clk_regs = top_clk_regs,
322 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
323};
324
325static void __init exynos850_cmu_top_init(struct device_node *np)
326{
327 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
328}
329
330/* Register CMU_TOP early, as it's a dependency for other early domains */
331CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
332 exynos850_cmu_top_init);
333
334/* ---- CMU_APM ------------------------------------------------------------- */
335
336/* Register Offset definitions for CMU_APM (0x11800000) */
337#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
338#define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
339#define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
340#define PLL_CON0_MUX_DLL_USER 0x0630
341#define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
342#define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
343#define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
344#define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
345#define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
346#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
347#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
348#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
349#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
350#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
351#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
352#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
353#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
354#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
355#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
356#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
357
358static const unsigned long apm_clk_regs[] __initconst = {
359 PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
360 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
361 PLL_CON0_MUX_CLK_RCO_APM_USER,
362 PLL_CON0_MUX_DLL_USER,
363 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
364 CLK_CON_MUX_MUX_CLK_APM_BUS,
365 CLK_CON_MUX_MUX_CLK_APM_I3C,
366 CLK_CON_DIV_CLKCMU_CHUB_BUS,
367 CLK_CON_DIV_DIV_CLK_APM_BUS,
368 CLK_CON_DIV_DIV_CLK_APM_I3C,
369 CLK_CON_GAT_CLKCMU_CMGP_BUS,
370 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
371 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
372 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
373 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
374 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
375 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
376 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
377 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
378 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
379};
380
381/* List of parent clocks for Muxes in CMU_APM */
382PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
383PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
384PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
385PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
386PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
387PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
388 "mout_dll_user", "oscclk_rco_apm" };
389PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
390
391static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
392 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
393 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
394 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
395 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
396};
397
398static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
399 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
400 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
401 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
402 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
403 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
404 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
405 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
406 PLL_CON0_MUX_DLL_USER, 4, 1),
407 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
408 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
409 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
410 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
411 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
412 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
413};
414
415static const struct samsung_div_clock apm_div_clks[] __initconst = {
416 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
417 "gout_clkcmu_chub_bus",
418 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
419 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
420 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
421 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
422 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
423};
424
425static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
426 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
427 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
428 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
429 "mout_clkcmu_chub_bus",
430 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
431 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
432 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
433 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
434 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
435 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
436 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
437 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
438 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
439 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
440 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
441 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
442 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
443 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
444 0),
445 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
446 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
447 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
448 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
449};
450
451static const struct samsung_cmu_info apm_cmu_info __initconst = {
452 .mux_clks = apm_mux_clks,
453 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
454 .div_clks = apm_div_clks,
455 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
456 .gate_clks = apm_gate_clks,
457 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
458 .fixed_clks = apm_fixed_clks,
459 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
460 .nr_clk_ids = APM_NR_CLK,
461 .clk_regs = apm_clk_regs,
462 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
463 .clk_name = "dout_clkcmu_apm_bus",
464};
465
466/* ---- CMU_CMGP ------------------------------------------------------------ */
467
468/* Register Offset definitions for CMU_CMGP (0x11c00000) */
469#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
470#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
471#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
472#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
473#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
474#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
475#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
476#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
477#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
478#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
479#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
480#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
481#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
482#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
483
484static const unsigned long cmgp_clk_regs[] __initconst = {
485 CLK_CON_MUX_CLK_CMGP_ADC,
486 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
487 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
488 CLK_CON_DIV_DIV_CLK_CMGP_ADC,
489 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
490 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
491 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
492 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
493 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
494 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
495 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
496 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
497 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
498 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
499};
500
501/* List of parent clocks for Muxes in CMU_CMGP */
502PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
503PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
504PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
505
506static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
507 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
508};
509
510static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
511 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
512 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
513 MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
514 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
515 MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
516 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
517};
518
519static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
520 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
521 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
522 DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
523 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
524 DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
525 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
526};
527
528static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
529 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
530 "gout_clkcmu_cmgp_bus",
531 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
532 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
533 "gout_clkcmu_cmgp_bus",
534 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
535 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
536 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
537 "gout_clkcmu_cmgp_bus",
538 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
539 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
540 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
541 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
542 "gout_clkcmu_cmgp_bus",
543 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
544 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
545 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
546 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
547 "gout_clkcmu_cmgp_bus",
548 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
549 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
550 "gout_clkcmu_cmgp_bus",
551 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
552};
553
554static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
555 .mux_clks = cmgp_mux_clks,
556 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
557 .div_clks = cmgp_div_clks,
558 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
559 .gate_clks = cmgp_gate_clks,
560 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
561 .fixed_clks = cmgp_fixed_clks,
562 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
563 .nr_clk_ids = CMGP_NR_CLK,
564 .clk_regs = cmgp_clk_regs,
565 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
566 .clk_name = "gout_clkcmu_cmgp_bus",
567};
568
569/* ---- CMU_HSI ------------------------------------------------------------- */
570
571/* Register Offset definitions for CMU_HSI (0x13400000) */
572#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
573#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
574#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
575#define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
576#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
577#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
578#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
579#define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
580#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
581#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
582#define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
583#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
584#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
585
586static const unsigned long hsi_clk_regs[] __initconst = {
587 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
588 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
589 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
590 CLK_CON_MUX_MUX_CLK_HSI_RTC,
591 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
592 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
593 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
594 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
595 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
596 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
597 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
598 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
599 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
600};
601
602/* List of parent clocks for Muxes in CMU_PERI */
603PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
604PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
605PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
606PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
607
608static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
609 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
610 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
611 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
612 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
613 4, 1, CLK_SET_RATE_PARENT, 0),
614 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
615 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
616 4, 1),
617 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
618 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
619};
620
621static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
622 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
623 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
624 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
625 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
626 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
627 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
628 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
629 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
630 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
631 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
632 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
633 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
634 "mout_hsi_mmc_card_user",
635 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
636 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
637 "mout_hsi_bus_user",
638 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
639 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
640 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
641 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
642 "mout_hsi_bus_user",
643 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
644};
645
646static const struct samsung_cmu_info hsi_cmu_info __initconst = {
647 .mux_clks = hsi_mux_clks,
648 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
649 .gate_clks = hsi_gate_clks,
650 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
651 .nr_clk_ids = HSI_NR_CLK,
652 .clk_regs = hsi_clk_regs,
653 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
654 .clk_name = "dout_hsi_bus",
655};
656
657/* ---- CMU_PERI ------------------------------------------------------------ */
658
659/* Register Offset definitions for CMU_PERI (0x10030000) */
660#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
661#define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
662#define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
663#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
664#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
665#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
666#define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
667#define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
668#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
669#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
670#define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
671#define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
672#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
673#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
674#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
675#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
676#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
677#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
678#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
679#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
680#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
681#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
682#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
683#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
684#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
685#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
686#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
687#define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
688#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
689#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
690#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
691#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
692#define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
693#define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
694
695static const unsigned long peri_clk_regs[] __initconst = {
696 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
697 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
698 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
699 PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
700 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
701 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
702 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
703 CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
704 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
705 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
706 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
707 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
708 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
709 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
710 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
711 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
712 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
713 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
714 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
715 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
716 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
717 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
718 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
719 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
720 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
721 CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
722 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
723 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
724 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
725 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
726 CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
727 CLK_CON_GAT_GOUT_PERI_UART_PCLK,
728 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
729 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
730};
731
732/* List of parent clocks for Muxes in CMU_PERI */
733PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
734PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" };
735PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" };
736PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
737
738static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
739 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
740 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
741 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
742 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
743 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
744 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
745 MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
746 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
747};
748
749static const struct samsung_div_clock peri_div_clks[] __initconst = {
750 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
751 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
752 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
753 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
754 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
755 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
756 DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
757 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
758};
759
760static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
761 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
762 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
763 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
764 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
765 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
766 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
767 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
768 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
769 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
770 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
771 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
772 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
773 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
774 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
775 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
776 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
777 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
778 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
779 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
780 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
781 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
782 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
783 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
784 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
785 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
786 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
787 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
788 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
789 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
790 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
791 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
792 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
793 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
794 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
795 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
796 "mout_peri_bus_user",
797 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
798 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
799 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
800 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
801 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
802 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
803 "mout_peri_bus_user",
804 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
805 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
806 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
807 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
808 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
809 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
810 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
811 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
812 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
813 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
814 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
815 "mout_peri_bus_user",
816 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
817};
818
819static const struct samsung_cmu_info peri_cmu_info __initconst = {
820 .mux_clks = peri_mux_clks,
821 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
822 .div_clks = peri_div_clks,
823 .nr_div_clks = ARRAY_SIZE(peri_div_clks),
824 .gate_clks = peri_gate_clks,
825 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
826 .nr_clk_ids = PERI_NR_CLK,
827 .clk_regs = peri_clk_regs,
828 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
829 .clk_name = "dout_peri_bus",
830};
831
832static void __init exynos850_cmu_peri_init(struct device_node *np)
833{
834 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
835}
836
837/* Register CMU_PERI early, as it's needed for MCT timer */
838CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
839 exynos850_cmu_peri_init);
840
841/* ---- CMU_CORE ------------------------------------------------------------ */
842
843/* Register Offset definitions for CMU_CORE (0x12000000) */
844#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
845#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
846#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
847#define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
848#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
849#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
850#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
851#define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
852#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
853#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
854#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
855#define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
856#define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
857#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
858
859static const unsigned long core_clk_regs[] __initconst = {
860 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
861 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
862 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
863 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
864 CLK_CON_MUX_MUX_CLK_CORE_GIC,
865 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
866 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
867 CLK_CON_GAT_GOUT_CORE_GIC_CLK,
868 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
869 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
870 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
871 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
872 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
873 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
874};
875
876/* List of parent clocks for Muxes in CMU_CORE */
877PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
878PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
879PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" };
880PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" };
881PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
882
883static const struct samsung_mux_clock core_mux_clks[] __initconst = {
884 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
885 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
886 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
887 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
888 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
889 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
890 4, 1, CLK_SET_RATE_PARENT, 0),
891 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
892 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
893 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
894 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
895};
896
897static const struct samsung_div_clock core_div_clks[] __initconst = {
898 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
899 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
900};
901
902static const struct samsung_gate_clock core_gate_clks[] __initconst = {
903 /* CCI (interconnect) clock must be always running */
904 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
905 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
906 /* GIC (interrupt controller) clock must be always running */
907 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
908 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
909 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
910 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
911 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
912 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
913 21, CLK_SET_RATE_PARENT, 0),
914 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
915 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
916 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
917 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
918 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
919 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
920 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
921 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
922 "dout_core_busp",
923 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
924};
925
926static const struct samsung_cmu_info core_cmu_info __initconst = {
927 .mux_clks = core_mux_clks,
928 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
929 .div_clks = core_div_clks,
930 .nr_div_clks = ARRAY_SIZE(core_div_clks),
931 .gate_clks = core_gate_clks,
932 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
933 .nr_clk_ids = CORE_NR_CLK,
934 .clk_regs = core_clk_regs,
935 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
936 .clk_name = "dout_core_bus",
937};
938
939/* ---- CMU_DPU ------------------------------------------------------------- */
940
941/* Register Offset definitions for CMU_DPU (0x13000000) */
942#define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
943#define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
944#define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
945#define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
946#define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
947#define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
948#define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
949#define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
950#define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
951#define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
952
953static const unsigned long dpu_clk_regs[] __initconst = {
954 PLL_CON0_MUX_CLKCMU_DPU_USER,
955 CLK_CON_DIV_DIV_CLK_DPU_BUSP,
956 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
957 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
958 CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
959 CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
960 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
961 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
962 CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
963 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
964};
965
966/* List of parent clocks for Muxes in CMU_CORE */
967PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
968
969static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
970 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
971 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
972};
973
974static const struct samsung_div_clock dpu_div_clks[] __initconst = {
975 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
976 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
977};
978
979static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
980 /* TODO: Should be enabled in DSIM driver */
981 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
982 "dout_dpu_busp",
983 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
984 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
985 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
986 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
987 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
988 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
989 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
990 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
991 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
992 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
993 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
994 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
995 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
996 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
997 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
998};
999
1000static const struct samsung_cmu_info dpu_cmu_info __initconst = {
1001 .mux_clks = dpu_mux_clks,
1002 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
1003 .div_clks = dpu_div_clks,
1004 .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
1005 .gate_clks = dpu_gate_clks,
1006 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
1007 .nr_clk_ids = DPU_NR_CLK,
1008 .clk_regs = dpu_clk_regs,
1009 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
1010 .clk_name = "dout_dpu",
1011};
1012
1013/* ---- platform_driver ----------------------------------------------------- */
1014
1015static int __init exynos850_cmu_probe(struct platform_device *pdev)
1016{
1017 const struct samsung_cmu_info *info;
1018 struct device *dev = &pdev->dev;
1019
1020 info = of_device_get_match_data(dev);
1021 exynos_arm64_register_cmu(dev, dev->of_node, info);
1022
1023 return 0;
1024}
1025
1026static const struct of_device_id exynos850_cmu_of_match[] = {
1027 {
1028 .compatible = "samsung,exynos850-cmu-apm",
1029 .data = &apm_cmu_info,
1030 }, {
1031 .compatible = "samsung,exynos850-cmu-cmgp",
1032 .data = &cmgp_cmu_info,
1033 }, {
1034 .compatible = "samsung,exynos850-cmu-hsi",
1035 .data = &hsi_cmu_info,
1036 }, {
1037 .compatible = "samsung,exynos850-cmu-core",
1038 .data = &core_cmu_info,
1039 }, {
1040 .compatible = "samsung,exynos850-cmu-dpu",
1041 .data = &dpu_cmu_info,
1042 }, {
1043 },
1044};
1045
1046static struct platform_driver exynos850_cmu_driver __refdata = {
1047 .driver = {
1048 .name = "exynos850-cmu",
1049 .of_match_table = exynos850_cmu_of_match,
1050 .suppress_bind_attrs = true,
1051 },
1052 .probe = exynos850_cmu_probe,
1053};
1054
1055static int __init exynos850_cmu_init(void)
1056{
1057 return platform_driver_register(&exynos850_cmu_driver);
1058}
1059core_initcall(exynos850_cmu_init);