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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
3
4#ifndef __QCOM_CLK_ALPHA_PLL_H__
5#define __QCOM_CLK_ALPHA_PLL_H__
6
7#include <linux/clk-provider.h>
8#include "clk-regmap.h"
9
10/* Alpha PLL types */
11enum {
12 CLK_ALPHA_PLL_TYPE_DEFAULT,
13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
17 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
18 CLK_ALPHA_PLL_TYPE_AGERA,
19 CLK_ALPHA_PLL_TYPE_ZONDA,
20 CLK_ALPHA_PLL_TYPE_LUCID_EVO,
21 CLK_ALPHA_PLL_TYPE_MAX,
22};
23
24enum {
25 PLL_OFF_L_VAL,
26 PLL_OFF_CAL_L_VAL,
27 PLL_OFF_ALPHA_VAL,
28 PLL_OFF_ALPHA_VAL_U,
29 PLL_OFF_USER_CTL,
30 PLL_OFF_USER_CTL_U,
31 PLL_OFF_USER_CTL_U1,
32 PLL_OFF_CONFIG_CTL,
33 PLL_OFF_CONFIG_CTL_U,
34 PLL_OFF_CONFIG_CTL_U1,
35 PLL_OFF_TEST_CTL,
36 PLL_OFF_TEST_CTL_U,
37 PLL_OFF_TEST_CTL_U1,
38 PLL_OFF_STATUS,
39 PLL_OFF_OPMODE,
40 PLL_OFF_FRAC,
41 PLL_OFF_CAL_VAL,
42 PLL_OFF_MAX_REGS
43};
44
45extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
46
47struct pll_vco {
48 unsigned long min_freq;
49 unsigned long max_freq;
50 u32 val;
51};
52
53#define VCO(a, b, c) { \
54 .val = a,\
55 .min_freq = b,\
56 .max_freq = c,\
57}
58
59/**
60 * struct clk_alpha_pll - phase locked loop (PLL)
61 * @offset: base address of registers
62 * @vco_table: array of VCO settings
63 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
64 * @clkr: regmap clock handle
65 */
66struct clk_alpha_pll {
67 u32 offset;
68 const u8 *regs;
69
70 const struct pll_vco *vco_table;
71 size_t num_vco;
72#define SUPPORTS_OFFLINE_REQ BIT(0)
73#define SUPPORTS_FSM_MODE BIT(2)
74#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
75 u8 flags;
76
77 struct clk_regmap clkr;
78};
79
80/**
81 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
82 * @offset: base address of registers
83 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
84 * @width: width of post-divider
85 * @post_div_shift: shift to differentiate between odd & even post-divider
86 * @post_div_table: table with PLL odd and even post-divider settings
87 * @num_post_div: Number of PLL post-divider settings
88 *
89 * @clkr: regmap clock handle
90 */
91struct clk_alpha_pll_postdiv {
92 u32 offset;
93 u8 width;
94 const u8 *regs;
95
96 struct clk_regmap clkr;
97 int post_div_shift;
98 const struct clk_div_table *post_div_table;
99 size_t num_post_div;
100};
101
102struct alpha_pll_config {
103 u32 l;
104 u32 alpha;
105 u32 alpha_hi;
106 u32 config_ctl_val;
107 u32 config_ctl_hi_val;
108 u32 config_ctl_hi1_val;
109 u32 user_ctl_val;
110 u32 user_ctl_hi_val;
111 u32 user_ctl_hi1_val;
112 u32 test_ctl_val;
113 u32 test_ctl_hi_val;
114 u32 test_ctl_hi1_val;
115 u32 main_output_mask;
116 u32 aux_output_mask;
117 u32 aux2_output_mask;
118 u32 early_output_mask;
119 u32 alpha_en_mask;
120 u32 alpha_mode_mask;
121 u32 pre_div_val;
122 u32 pre_div_mask;
123 u32 post_div_val;
124 u32 post_div_mask;
125 u32 vco_val;
126 u32 vco_mask;
127};
128
129extern const struct clk_ops clk_alpha_pll_ops;
130extern const struct clk_ops clk_alpha_pll_fixed_ops;
131extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
132extern const struct clk_ops clk_alpha_pll_postdiv_ops;
133extern const struct clk_ops clk_alpha_pll_huayra_ops;
134extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
135
136extern const struct clk_ops clk_alpha_pll_fabia_ops;
137extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
138extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
139
140extern const struct clk_ops clk_alpha_pll_trion_ops;
141extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
142extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
143
144extern const struct clk_ops clk_alpha_pll_lucid_ops;
145#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
146extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
147extern const struct clk_ops clk_alpha_pll_agera_ops;
148
149extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
150extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
151extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
152
153extern const struct clk_ops clk_alpha_pll_zonda_ops;
154#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
155extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
156extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
157
158void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
159 const struct alpha_pll_config *config);
160void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
161 const struct alpha_pll_config *config);
162void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
163 const struct alpha_pll_config *config);
164void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
165 const struct alpha_pll_config *config);
166#define clk_lucid_pll_configure(pll, regmap, config) \
167 clk_trion_pll_configure(pll, regmap, config)
168
169void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
170 const struct alpha_pll_config *config);
171
172
173#endif