tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <asm/asm-compat.h>
9#include <asm/processor.h>
10#include <asm/ppc-opcode.h>
11#include <asm/firmware.h>
12#include <asm/feature-fixups.h>
13#include <asm/extable.h>
14
15#ifdef __ASSEMBLY__
16
17#define SZL (BITS_PER_LONG/8)
18
19/*
20 * This expands to a sequence of operations with reg incrementing from
21 * start to end inclusive, of this form:
22 *
23 * op reg, (offset + (width * reg))(base)
24 *
25 * Note that offset is not the offset of the first operation unless start
26 * is zero (or width is zero).
27 */
28.macro OP_REGS op, width, start, end, base, offset
29 .Lreg=\start
30 .rept (\end - \start + 1)
31 \op .Lreg, \offset + \width * .Lreg(\base)
32 .Lreg=.Lreg+1
33 .endr
34.endm
35
36/*
37 * Macros for storing registers into and loading registers from
38 * exception frames.
39 */
40#ifdef __powerpc64__
41#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
42#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
43#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
44#define REST_NVGPRS(base) REST_GPRS(14, 31, base)
45#else
46#define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0
47#define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0
48#define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base)
49#define REST_NVGPRS(base) REST_GPRS(13, 31, base)
50#endif
51
52#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base)
53#define REST_GPR(n, base) REST_GPRS(n, n, base)
54
55#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base)
56#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
57#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
58#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
59#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
60#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
61#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base)
62#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
63#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
64#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
65#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
66#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
67
68#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b
69#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
70#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
71#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
72#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
73#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
74#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b
75#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
76#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
77#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
78#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
79#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
80
81#ifdef __BIG_ENDIAN__
82#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base)
83#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base)
84#else
85#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \
86 STXVD2X(n,b,base); \
87 XXSWAPD(n,n)
88
89#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \
90 XXSWAPD(n,n)
91#endif
92/* Save the lower 32 VSRs in the thread VSR region */
93#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b)
94#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
95#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
96#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
97#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
98#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
99#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
100#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
101#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
102#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
103#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
104#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
105
106/*
107 * b = base register for addressing, o = base offset from register of 1st EVR
108 * n = first EVR, s = scratch
109 */
110#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
111#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
112#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
113#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
114#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
115#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
116#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
117#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
118#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
119#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
120#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
121#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
122
123/* Macros to adjust thread priority for hardware multithreading */
124#define HMT_VERY_LOW or 31,31,31 # very low priority
125#define HMT_LOW or 1,1,1
126#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
127#define HMT_MEDIUM or 2,2,2
128#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
129#define HMT_HIGH or 3,3,3
130#define HMT_EXTRA_HIGH or 7,7,7 # power7 only
131
132#ifdef CONFIG_PPC64
133#define ULONG_SIZE 8
134#else
135#define ULONG_SIZE 4
136#endif
137#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE))
138#define VCPU_GPR(n) __VCPU_GPR(__REG_##n)
139
140#ifdef __KERNEL__
141
142/*
143 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
144 * version below in the else case of the ifdef.
145 */
146#ifdef __powerpc64__
147
148#define STACKFRAMESIZE 256
149#define __STK_REG(i) (112 + ((i)-14)*8)
150#define STK_REG(i) __STK_REG(__REG_##i)
151
152#ifdef PPC64_ELF_ABI_v2
153#define STK_GOT 24
154#define __STK_PARAM(i) (32 + ((i)-3)*8)
155#else
156#define STK_GOT 40
157#define __STK_PARAM(i) (48 + ((i)-3)*8)
158#endif
159#define STK_PARAM(i) __STK_PARAM(__REG_##i)
160
161#ifdef PPC64_ELF_ABI_v2
162
163#define _GLOBAL(name) \
164 .align 2 ; \
165 .type name,@function; \
166 .globl name; \
167name:
168
169#define _GLOBAL_TOC(name) \
170 .align 2 ; \
171 .type name,@function; \
172 .globl name; \
173name: \
1740: addis r2,r12,(.TOC.-0b)@ha; \
175 addi r2,r2,(.TOC.-0b)@l; \
176 .localentry name,.-name
177
178#define DOTSYM(a) a
179
180#else
181
182#define XGLUE(a,b) a##b
183#define GLUE(a,b) XGLUE(a,b)
184
185#define _GLOBAL(name) \
186 .align 2 ; \
187 .globl name; \
188 .globl GLUE(.,name); \
189 .pushsection ".opd","aw"; \
190name: \
191 .quad GLUE(.,name); \
192 .quad .TOC.@tocbase; \
193 .quad 0; \
194 .popsection; \
195 .type GLUE(.,name),@function; \
196GLUE(.,name):
197
198#define _GLOBAL_TOC(name) _GLOBAL(name)
199
200#define DOTSYM(a) GLUE(.,a)
201
202#endif
203
204#else /* 32-bit */
205
206#define _ENTRY(n) \
207 .globl n; \
208n:
209
210#define _GLOBAL(n) \
211 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
212 .globl n; \
213n:
214
215#define _GLOBAL_TOC(name) _GLOBAL(name)
216
217#define DOTSYM(a) a
218
219#endif
220
221/*
222 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
223 * section, which gets emitted at the end of regular text.
224 *
225 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
226 * a blacklist. The former is for core kprobe functions/data, the
227 * latter is for those that incdentially must be excluded from probing
228 * and allows them to be linked at more optimal location within text.
229 */
230#ifdef CONFIG_KPROBES
231#define _ASM_NOKPROBE_SYMBOL(entry) \
232 .pushsection "_kprobe_blacklist","aw"; \
233 PPC_LONG (entry) ; \
234 .popsection
235#else
236#define _ASM_NOKPROBE_SYMBOL(entry)
237#endif
238
239#define FUNC_START(name) _GLOBAL(name)
240#define FUNC_END(name)
241
242/*
243 * LOAD_REG_IMMEDIATE(rn, expr)
244 * Loads the value of the constant expression 'expr' into register 'rn'
245 * using immediate instructions only. Use this when it's important not
246 * to reference other data (i.e. on ppc64 when the TOC pointer is not
247 * valid) and when 'expr' is a constant or absolute address.
248 *
249 * LOAD_REG_ADDR(rn, name)
250 * Loads the address of label 'name' into register 'rn'. Use this when
251 * you don't particularly need immediate instructions only, but you need
252 * the whole address in one register (e.g. it's a structure address and
253 * you want to access various offsets within it). On ppc32 this is
254 * identical to LOAD_REG_IMMEDIATE.
255 *
256 * LOAD_REG_ADDR_PIC(rn, name)
257 * Loads the address of label 'name' into register 'run'. Use this when
258 * the kernel doesn't run at the linked or relocated address. Please
259 * note that this macro will clobber the lr register.
260 *
261 * LOAD_REG_ADDRBASE(rn, name)
262 * ADDROFF(name)
263 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
264 * register 'rn'. ADDROFF(name) returns the remainder of the address as
265 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
266 * in size, so is suitable for use directly as an offset in load and store
267 * instructions. Use this when loading/storing a single word or less as:
268 * LOAD_REG_ADDRBASE(rX, name)
269 * ld rY,ADDROFF(name)(rX)
270 */
271
272/* Be careful, this will clobber the lr register. */
273#define LOAD_REG_ADDR_PIC(reg, name) \
274 bcl 20,31,$+4; \
2750: mflr reg; \
276 addis reg,reg,(name - 0b)@ha; \
277 addi reg,reg,(name - 0b)@l;
278
279#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
280#define __AS_ATHIGH high
281#else
282#define __AS_ATHIGH h
283#endif
284
285.macro __LOAD_REG_IMMEDIATE_32 r, x
286 .if (\x) >= 0x8000 || (\x) < -0x8000
287 lis \r, (\x)@__AS_ATHIGH
288 .if (\x) & 0xffff != 0
289 ori \r, \r, (\x)@l
290 .endif
291 .else
292 li \r, (\x)@l
293 .endif
294.endm
295
296.macro __LOAD_REG_IMMEDIATE r, x
297 .if (\x) >= 0x80000000 || (\x) < -0x80000000
298 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
299 sldi \r, \r, 32
300 .if (\x) & 0xffff0000 != 0
301 oris \r, \r, (\x)@__AS_ATHIGH
302 .endif
303 .if (\x) & 0xffff != 0
304 ori \r, \r, (\x)@l
305 .endif
306 .else
307 __LOAD_REG_IMMEDIATE_32 \r, \x
308 .endif
309.endm
310
311#ifdef __powerpc64__
312
313#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
314
315#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \
316 lis tmp, (expr)@highest; \
317 lis reg, (expr)@__AS_ATHIGH; \
318 ori tmp, tmp, (expr)@higher; \
319 ori reg, reg, (expr)@l; \
320 rldimi reg, tmp, 32, 0
321
322#define LOAD_REG_ADDR(reg,name) \
323 ld reg,name@got(r2)
324
325#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
326#define ADDROFF(name) 0
327
328/* offsets for stack frame layout */
329#define LRSAVE 16
330
331#else /* 32-bit */
332
333#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
334
335#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \
336 lis reg,(expr)@ha; \
337 addi reg,reg,(expr)@l;
338
339#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name)
340
341#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha
342#define ADDROFF(name) name@l
343
344/* offsets for stack frame layout */
345#define LRSAVE 4
346
347#endif
348
349/* various errata or part fixups */
350#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
351#define MFTB(dest) \
35290: mfspr dest, SPRN_TBRL; \
353BEGIN_FTR_SECTION_NESTED(96); \
354 cmpwi dest,0; \
355 beq- 90b; \
356END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
357#else
358#define MFTB(dest) MFTBL(dest)
359#endif
360
361#ifdef CONFIG_PPC_8xx
362#define MFTBL(dest) mftb dest
363#define MFTBU(dest) mftbu dest
364#else
365#define MFTBL(dest) mfspr dest, SPRN_TBRL
366#define MFTBU(dest) mfspr dest, SPRN_TBRU
367#endif
368
369#ifndef CONFIG_SMP
370#define TLBSYNC
371#else
372#define TLBSYNC tlbsync; sync
373#endif
374
375#ifdef CONFIG_PPC64
376#define MTOCRF(FXM, RS) \
377 BEGIN_FTR_SECTION_NESTED(848); \
378 mtcrf (FXM), RS; \
379 FTR_SECTION_ELSE_NESTED(848); \
380 mtocrf (FXM), RS; \
381 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
382#endif
383
384/*
385 * This instruction is not implemented on the PPC 603 or 601; however, on
386 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
387 * All of these instructions exist in the 8xx, they have magical powers,
388 * and they must be used.
389 */
390
391#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
392#define tlbia \
393 li r4,1024; \
394 mtctr r4; \
395 lis r4,KERNELBASE@h; \
396 .machine push; \
397 .machine "power4"; \
3980: tlbie r4; \
399 .machine pop; \
400 addi r4,r4,0x1000; \
401 bdnz 0b
402#endif
403
404
405#ifdef CONFIG_IBM440EP_ERR42
406#define PPC440EP_ERR42 isync
407#else
408#define PPC440EP_ERR42
409#endif
410
411/* The following stops all load and store data streams associated with stream
412 * ID (ie. streams created explicitly). The embedded and server mnemonics for
413 * dcbt are different so this must only be used for server.
414 */
415#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \
416 lis scratch,0x60000000@h; \
417 dcbt 0,scratch,0b01010
418
419/*
420 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
421 * keep the address intact to be compatible with code shared with
422 * 32-bit classic.
423 *
424 * On the other hand, I find it useful to have them behave as expected
425 * by their name (ie always do the addition) on 64-bit BookE
426 */
427#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
428#define toreal(rd)
429#define fromreal(rd)
430
431/*
432 * We use addis to ensure compatibility with the "classic" ppc versions of
433 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
434 * converting the address in r0, and so this version has to do that too
435 * (i.e. set register rd to 0 when rs == 0).
436 */
437#define tophys(rd,rs) \
438 addis rd,rs,0
439
440#define tovirt(rd,rs) \
441 addis rd,rs,0
442
443#elif defined(CONFIG_PPC64)
444#define toreal(rd) /* we can access c000... in real mode */
445#define fromreal(rd)
446
447#define tophys(rd,rs) \
448 clrldi rd,rs,2
449
450#define tovirt(rd,rs) \
451 rotldi rd,rs,16; \
452 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
453 rotldi rd,rd,48
454#else
455#define toreal(rd) tophys(rd,rd)
456#define fromreal(rd) tovirt(rd,rd)
457
458#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h
459#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h
460#endif
461
462#ifdef CONFIG_PPC_BOOK3S_64
463#define MTMSRD(r) mtmsrd r
464#define MTMSR_EERI(reg) mtmsrd reg,1
465#else
466#define MTMSRD(r) mtmsr r
467#define MTMSR_EERI(reg) mtmsr reg
468#endif
469
470#endif /* __KERNEL__ */
471
472/* The boring bits... */
473
474/* Condition Register Bit Fields */
475
476#define cr0 0
477#define cr1 1
478#define cr2 2
479#define cr3 3
480#define cr4 4
481#define cr5 5
482#define cr6 6
483#define cr7 7
484
485
486/*
487 * General Purpose Registers (GPRs)
488 *
489 * The lower case r0-r31 should be used in preference to the upper
490 * case R0-R31 as they provide more error checking in the assembler.
491 * Use R0-31 only when really nessesary.
492 */
493
494#define r0 %r0
495#define r1 %r1
496#define r2 %r2
497#define r3 %r3
498#define r4 %r4
499#define r5 %r5
500#define r6 %r6
501#define r7 %r7
502#define r8 %r8
503#define r9 %r9
504#define r10 %r10
505#define r11 %r11
506#define r12 %r12
507#define r13 %r13
508#define r14 %r14
509#define r15 %r15
510#define r16 %r16
511#define r17 %r17
512#define r18 %r18
513#define r19 %r19
514#define r20 %r20
515#define r21 %r21
516#define r22 %r22
517#define r23 %r23
518#define r24 %r24
519#define r25 %r25
520#define r26 %r26
521#define r27 %r27
522#define r28 %r28
523#define r29 %r29
524#define r30 %r30
525#define r31 %r31
526
527
528/* Floating Point Registers (FPRs) */
529
530#define fr0 0
531#define fr1 1
532#define fr2 2
533#define fr3 3
534#define fr4 4
535#define fr5 5
536#define fr6 6
537#define fr7 7
538#define fr8 8
539#define fr9 9
540#define fr10 10
541#define fr11 11
542#define fr12 12
543#define fr13 13
544#define fr14 14
545#define fr15 15
546#define fr16 16
547#define fr17 17
548#define fr18 18
549#define fr19 19
550#define fr20 20
551#define fr21 21
552#define fr22 22
553#define fr23 23
554#define fr24 24
555#define fr25 25
556#define fr26 26
557#define fr27 27
558#define fr28 28
559#define fr29 29
560#define fr30 30
561#define fr31 31
562
563/* AltiVec Registers (VPRs) */
564
565#define v0 0
566#define v1 1
567#define v2 2
568#define v3 3
569#define v4 4
570#define v5 5
571#define v6 6
572#define v7 7
573#define v8 8
574#define v9 9
575#define v10 10
576#define v11 11
577#define v12 12
578#define v13 13
579#define v14 14
580#define v15 15
581#define v16 16
582#define v17 17
583#define v18 18
584#define v19 19
585#define v20 20
586#define v21 21
587#define v22 22
588#define v23 23
589#define v24 24
590#define v25 25
591#define v26 26
592#define v27 27
593#define v28 28
594#define v29 29
595#define v30 30
596#define v31 31
597
598/* VSX Registers (VSRs) */
599
600#define vs0 0
601#define vs1 1
602#define vs2 2
603#define vs3 3
604#define vs4 4
605#define vs5 5
606#define vs6 6
607#define vs7 7
608#define vs8 8
609#define vs9 9
610#define vs10 10
611#define vs11 11
612#define vs12 12
613#define vs13 13
614#define vs14 14
615#define vs15 15
616#define vs16 16
617#define vs17 17
618#define vs18 18
619#define vs19 19
620#define vs20 20
621#define vs21 21
622#define vs22 22
623#define vs23 23
624#define vs24 24
625#define vs25 25
626#define vs26 26
627#define vs27 27
628#define vs28 28
629#define vs29 29
630#define vs30 30
631#define vs31 31
632#define vs32 32
633#define vs33 33
634#define vs34 34
635#define vs35 35
636#define vs36 36
637#define vs37 37
638#define vs38 38
639#define vs39 39
640#define vs40 40
641#define vs41 41
642#define vs42 42
643#define vs43 43
644#define vs44 44
645#define vs45 45
646#define vs46 46
647#define vs47 47
648#define vs48 48
649#define vs49 49
650#define vs50 50
651#define vs51 51
652#define vs52 52
653#define vs53 53
654#define vs54 54
655#define vs55 55
656#define vs56 56
657#define vs57 57
658#define vs58 58
659#define vs59 59
660#define vs60 60
661#define vs61 61
662#define vs62 62
663#define vs63 63
664
665/* SPE Registers (EVPRs) */
666
667#define evr0 0
668#define evr1 1
669#define evr2 2
670#define evr3 3
671#define evr4 4
672#define evr5 5
673#define evr6 6
674#define evr7 7
675#define evr8 8
676#define evr9 9
677#define evr10 10
678#define evr11 11
679#define evr12 12
680#define evr13 13
681#define evr14 14
682#define evr15 15
683#define evr16 16
684#define evr17 17
685#define evr18 18
686#define evr19 19
687#define evr20 20
688#define evr21 21
689#define evr22 22
690#define evr23 23
691#define evr24 24
692#define evr25 25
693#define evr26 26
694#define evr27 27
695#define evr28 28
696#define evr29 29
697#define evr30 30
698#define evr31 31
699
700/* some stab codes */
701#define N_FUN 36
702#define N_RSYM 64
703#define N_SLINE 68
704#define N_SO 100
705
706#define RFSCV .long 0x4c0000a4
707
708/*
709 * Create an endian fixup trampoline
710 *
711 * This starts with a "tdi 0,0,0x48" instruction which is
712 * essentially a "trap never", and thus akin to a nop.
713 *
714 * The opcode for this instruction read with the wrong endian
715 * however results in a b . + 8
716 *
717 * So essentially we use that trick to execute the following
718 * trampoline in "reverse endian" if we are running with the
719 * MSR_LE bit set the "wrong" way for whatever endianness the
720 * kernel is built for.
721 */
722
723#ifdef CONFIG_PPC_BOOK3E
724#define FIXUP_ENDIAN
725#else
726/*
727 * This version may be used in HV or non-HV context.
728 * MSR[EE] must be disabled.
729 */
730#define FIXUP_ENDIAN \
731 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
732 b 191f; /* Skip trampoline if endian is good */ \
733 .long 0xa600607d; /* mfmsr r11 */ \
734 .long 0x01006b69; /* xori r11,r11,1 */ \
735 .long 0x00004039; /* li r10,0 */ \
736 .long 0x6401417d; /* mtmsrd r10,1 */ \
737 .long 0x05009f42; /* bcl 20,31,$+4 */ \
738 .long 0xa602487d; /* mflr r10 */ \
739 .long 0x14004a39; /* addi r10,r10,20 */ \
740 .long 0xa6035a7d; /* mtsrr0 r10 */ \
741 .long 0xa6037b7d; /* mtsrr1 r11 */ \
742 .long 0x2400004c; /* rfid */ \
743191:
744
745/*
746 * This version that may only be used with MSR[HV]=1
747 * - Does not clear MSR[RI], so more robust.
748 * - Slightly smaller and faster.
749 */
750#define FIXUP_ENDIAN_HV \
751 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
752 b 191f; /* Skip trampoline if endian is good */ \
753 .long 0xa600607d; /* mfmsr r11 */ \
754 .long 0x01006b69; /* xori r11,r11,1 */ \
755 .long 0x05009f42; /* bcl 20,31,$+4 */ \
756 .long 0xa602487d; /* mflr r10 */ \
757 .long 0x14004a39; /* addi r10,r10,20 */ \
758 .long 0xa64b5a7d; /* mthsrr0 r10 */ \
759 .long 0xa64b7b7d; /* mthsrr1 r11 */ \
760 .long 0x2402004c; /* hrfid */ \
761191:
762
763#endif /* !CONFIG_PPC_BOOK3E */
764
765#endif /* __ASSEMBLY__ */
766
767#define SOFT_MASK_TABLE(_start, _end) \
768 stringify_in_c(.section __soft_mask_table,"a";)\
769 stringify_in_c(.balign 8;) \
770 stringify_in_c(.llong (_start);) \
771 stringify_in_c(.llong (_end);) \
772 stringify_in_c(.previous)
773
774#define RESTART_TABLE(_start, _end, _target) \
775 stringify_in_c(.section __restart_table,"a";)\
776 stringify_in_c(.balign 8;) \
777 stringify_in_c(.llong (_start);) \
778 stringify_in_c(.llong (_end);) \
779 stringify_in_c(.llong (_target);) \
780 stringify_in_c(.previous)
781
782#ifdef CONFIG_PPC_FSL_BOOK3E
783#define BTB_FLUSH(reg) \
784 lis reg,BUCSR_INIT@h; \
785 ori reg,reg,BUCSR_INIT@l; \
786 mtspr SPRN_BUCSR,reg; \
787 isync;
788#else
789#define BTB_FLUSH(reg)
790#endif /* CONFIG_PPC_FSL_BOOK3E */
791
792#endif /* _ASM_POWERPC_PPC_ASM_H */