tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10 - devicetree@vger.kernel.org
11
12allOf:
13 - $ref: serial.yaml#
14 - if:
15 anyOf:
16 - required:
17 - aspeed,lpc-io-reg
18 - required:
19 - aspeed,lpc-interrupts
20 - required:
21 - aspeed,sirq-polarity-sense
22 then:
23 properties:
24 compatible:
25 const: aspeed,ast2500-vuart
26 - if:
27 properties:
28 compatible:
29 const: mrvl,mmp-uart
30 then:
31 properties:
32 reg-shift:
33 const: 2
34 required:
35 - reg-shift
36 - if:
37 not:
38 properties:
39 compatible:
40 items:
41 - enum:
42 - ns8250
43 - ns16450
44 - ns16550
45 - ns16550a
46 then:
47 anyOf:
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
50
51properties:
52 compatible:
53 oneOf:
54 - const: ns8250
55 - const: ns16450
56 - const: ns16550
57 - const: ns16550a
58 - const: ns16850
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nvidia,tegra20-uart
66 - const: nxp,lpc3220-uart
67 - items:
68 - enum:
69 - exar,xr16l2552
70 - exar,xr16l2551
71 - exar,xr16l2550
72 - const: ns8250
73 - items:
74 - enum:
75 - altr,16550-FIFO32
76 - altr,16550-FIFO64
77 - altr,16550-FIFO128
78 - fsl,16550-FIFO64
79 - fsl,ns16550
80 - andestech,uart16550
81 - nxp,lpc1850-uart
82 - opencores,uart16550-rtlsvn105
83 - ti,da830-uart
84 - const: ns16550a
85 - items:
86 - enum:
87 - ns16750
88 - cavium,octeon-3860-uart
89 - xlnx,xps-uart16550-2.00.b
90 - ralink,rt2880-uart
91 - enum:
92 - ns16550 # Deprecated, unless the FIFO really is broken
93 - ns16550a
94 - items:
95 - enum:
96 - ralink,mt7620a-uart
97 - ralink,rt3052-uart
98 - ralink,rt3883-uart
99 - const: ralink,rt2880-uart
100 - enum:
101 - ns16550 # Deprecated, unless the FIFO really is broken
102 - ns16550a
103 - items:
104 - enum:
105 - mediatek,mt7622-btif
106 - mediatek,mt7623-btif
107 - const: mediatek,mtk-btif
108 - items:
109 - const: mrvl,mmp-uart
110 - const: intel,xscale-uart
111 - items:
112 - enum:
113 - nvidia,tegra30-uart
114 - nvidia,tegra114-uart
115 - nvidia,tegra124-uart
116 - nvidia,tegra210-uart
117 - nvidia,tegra186-uart
118 - nvidia,tegra194-uart
119 - nvidia,tegra234-uart
120 - const: nvidia,tegra20-uart
121
122 reg:
123 maxItems: 1
124
125 interrupts:
126 maxItems: 1
127
128 clock-frequency: true
129
130 clocks:
131 maxItems: 1
132
133 resets:
134 maxItems: 1
135
136 current-speed:
137 $ref: /schemas/types.yaml#/definitions/uint32
138 description: The current active speed of the UART.
139
140 reg-offset:
141 description: |
142 Offset to apply to the mapbase from the start of the registers.
143
144 reg-shift:
145 description: Quantity to shift the register offsets by.
146
147 reg-io-width:
148 description: |
149 The size (in bytes) of the IO accesses that should be performed on the
150 device. There are some systems that require 32-bit accesses to the
151 UART (e.g. TI davinci).
152
153 used-by-rtas:
154 type: boolean
155 description: |
156 Set to indicate that the port is in use by the OpenFirmware RTAS and
157 should not be registered.
158
159 no-loopback-test:
160 type: boolean
161 description: |
162 Set to indicate that the port does not implement loopback test mode.
163
164 fifo-size:
165 $ref: /schemas/types.yaml#/definitions/uint32
166 description: The fifo size of the UART.
167
168 auto-flow-control:
169 type: boolean
170 description: |
171 One way to enable automatic flow control support. The driver is
172 allowed to detect support for the capability even without this
173 property.
174
175 tx-threshold:
176 description: |
177 Specify the TX FIFO low water indication for parts with programmable
178 TX FIFO thresholds.
179
180 overrun-throttle-ms:
181 description: |
182 How long to pause uart rx when input overrun is encountered.
183
184 rts-gpios: true
185 cts-gpios: true
186 dtr-gpios: true
187 dsr-gpios: true
188 rng-gpios: true
189 dcd-gpios: true
190
191 aspeed,sirq-polarity-sense:
192 $ref: /schemas/types.yaml#/definitions/phandle-array
193 description: |
194 Phandle to aspeed,ast2500-scu compatible syscon alongside register
195 offset and bit number to identify how the SIRQ polarity should be
196 configured. One possible data source is the LPC/eSPI mode bit. Only
197 applicable to aspeed,ast2500-vuart.
198 deprecated: true
199
200 aspeed,lpc-io-reg:
201 $ref: '/schemas/types.yaml#/definitions/uint32'
202 description: |
203 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
204
205 aspeed,lpc-interrupts:
206 $ref: "/schemas/types.yaml#/definitions/uint32-array"
207 minItems: 2
208 maxItems: 2
209 description: |
210 A 2-cell property describing the VUART SIRQ number and SIRQ
211 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
212 applicable to aspeed,ast2500-vuart.
213
214required:
215 - reg
216 - interrupts
217
218unevaluatedProperties: false
219
220examples:
221 - |
222 serial@80230000 {
223 compatible = "ns8250";
224 reg = <0x80230000 0x100>;
225 interrupts = <10>;
226 reg-shift = <2>;
227 clock-frequency = <48000000>;
228 };
229 - |
230 #include <dt-bindings/gpio/gpio.h>
231 serial@49042000 {
232 compatible = "andestech,uart16550", "ns16550a";
233 reg = <0x49042000 0x400>;
234 interrupts = <80>;
235 clock-frequency = <48000000>;
236 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
237 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
238 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
239 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
240 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
241 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
242 };
243 - |
244 #include <dt-bindings/clock/aspeed-clock.h>
245 #include <dt-bindings/interrupt-controller/irq.h>
246 serial@1e787000 {
247 compatible = "aspeed,ast2500-vuart";
248 reg = <0x1e787000 0x40>;
249 reg-shift = <2>;
250 interrupts = <8>;
251 clocks = <&syscon ASPEED_CLK_APB>;
252 no-loopback-test;
253 aspeed,lpc-io-reg = <0x3f8>;
254 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
255 };
256
257...