tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#include <linux/err.h>
17
18#define ZYNQMP_PM_VERSION_MAJOR 1
19#define ZYNQMP_PM_VERSION_MINOR 0
20
21#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24#define ZYNQMP_TZ_VERSION_MAJOR 1
25#define ZYNQMP_TZ_VERSION_MINOR 0
26
27#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30/* SMC SIP service Call Function Identifier Prefix */
31#define PM_SIP_SVC 0xC2000000
32#define PM_GET_TRUSTZONE_VERSION 0xa03
33#define PM_SET_SUSPEND_MODE 0xa02
34#define GET_CALLBACK_DATA 0xa01
35
36/* Number of 32bits values in payload */
37#define PAYLOAD_ARG_CNT 4U
38
39/* Number of arguments for a callback */
40#define CB_ARG_CNT 4
41
42/* Payload size (consists of callback API ID + arguments) */
43#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
44
45#define ZYNQMP_PM_MAX_QOS 100U
46
47#define GSS_NUM_REGS (4)
48
49/* Node capabilities */
50#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
51#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
52#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
53#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
54
55/* Loader commands */
56#define PM_LOAD_PDI 0x701
57#define PDI_SRC_DDR 0xF
58
59/*
60 * Firmware FPGA Manager flags
61 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
62 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
63 */
64#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
65#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
66
67/*
68 * Node IDs for the Error Events.
69 */
70#define EVENT_ERROR_PMC_ERR1 (0x28100000U)
71#define EVENT_ERROR_PMC_ERR2 (0x28104000U)
72#define EVENT_ERROR_PSM_ERR1 (0x28108000U)
73#define EVENT_ERROR_PSM_ERR2 (0x2810C000U)
74
75enum pm_api_cb_id {
76 PM_INIT_SUSPEND_CB = 30,
77 PM_ACKNOWLEDGE_CB = 31,
78 PM_NOTIFY_CB = 32,
79};
80
81enum pm_api_id {
82 PM_GET_API_VERSION = 1,
83 PM_REGISTER_NOTIFIER = 5,
84 PM_SYSTEM_SHUTDOWN = 12,
85 PM_REQUEST_NODE = 13,
86 PM_RELEASE_NODE = 14,
87 PM_SET_REQUIREMENT = 15,
88 PM_RESET_ASSERT = 17,
89 PM_RESET_GET_STATUS = 18,
90 PM_MMIO_WRITE = 19,
91 PM_MMIO_READ = 20,
92 PM_PM_INIT_FINALIZE = 21,
93 PM_FPGA_LOAD = 22,
94 PM_FPGA_GET_STATUS = 23,
95 PM_GET_CHIPID = 24,
96 PM_PINCTRL_REQUEST = 28,
97 PM_PINCTRL_RELEASE = 29,
98 PM_PINCTRL_GET_FUNCTION = 30,
99 PM_PINCTRL_SET_FUNCTION = 31,
100 PM_PINCTRL_CONFIG_PARAM_GET = 32,
101 PM_PINCTRL_CONFIG_PARAM_SET = 33,
102 PM_IOCTL = 34,
103 PM_QUERY_DATA = 35,
104 PM_CLOCK_ENABLE = 36,
105 PM_CLOCK_DISABLE = 37,
106 PM_CLOCK_GETSTATE = 38,
107 PM_CLOCK_SETDIVIDER = 39,
108 PM_CLOCK_GETDIVIDER = 40,
109 PM_CLOCK_SETRATE = 41,
110 PM_CLOCK_GETRATE = 42,
111 PM_CLOCK_SETPARENT = 43,
112 PM_CLOCK_GETPARENT = 44,
113 PM_SECURE_AES = 47,
114 PM_FEATURE_CHECK = 63,
115};
116
117/* PMU-FW return status codes */
118enum pm_ret_status {
119 XST_PM_SUCCESS = 0,
120 XST_PM_NO_FEATURE = 19,
121 XST_PM_INTERNAL = 2000,
122 XST_PM_CONFLICT = 2001,
123 XST_PM_NO_ACCESS = 2002,
124 XST_PM_INVALID_NODE = 2003,
125 XST_PM_DOUBLE_REQ = 2004,
126 XST_PM_ABORT_SUSPEND = 2005,
127 XST_PM_MULT_USER = 2008,
128};
129
130enum pm_ioctl_id {
131 IOCTL_SD_DLL_RESET = 6,
132 IOCTL_SET_SD_TAPDELAY = 7,
133 IOCTL_SET_PLL_FRAC_MODE = 8,
134 IOCTL_GET_PLL_FRAC_MODE = 9,
135 IOCTL_SET_PLL_FRAC_DATA = 10,
136 IOCTL_GET_PLL_FRAC_DATA = 11,
137 IOCTL_WRITE_GGS = 12,
138 IOCTL_READ_GGS = 13,
139 IOCTL_WRITE_PGGS = 14,
140 IOCTL_READ_PGGS = 15,
141 /* Set healthy bit value */
142 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
143 IOCTL_OSPI_MUX_SELECT = 21,
144 /* Register SGI to ATF */
145 IOCTL_REGISTER_SGI = 25,
146};
147
148enum pm_query_id {
149 PM_QID_INVALID = 0,
150 PM_QID_CLOCK_GET_NAME = 1,
151 PM_QID_CLOCK_GET_TOPOLOGY = 2,
152 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
153 PM_QID_CLOCK_GET_PARENTS = 4,
154 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
155 PM_QID_PINCTRL_GET_NUM_PINS = 6,
156 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
157 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
158 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
159 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
160 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
161 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
162 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
163};
164
165enum zynqmp_pm_reset_action {
166 PM_RESET_ACTION_RELEASE = 0,
167 PM_RESET_ACTION_ASSERT = 1,
168 PM_RESET_ACTION_PULSE = 2,
169};
170
171enum zynqmp_pm_reset {
172 ZYNQMP_PM_RESET_START = 1000,
173 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
174 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
175 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
176 ZYNQMP_PM_RESET_DP = 1003,
177 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
178 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
179 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
180 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
181 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
182 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
183 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
184 ZYNQMP_PM_RESET_GDMA = 1011,
185 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
186 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
187 ZYNQMP_PM_RESET_GPU = 1014,
188 ZYNQMP_PM_RESET_GT = 1015,
189 ZYNQMP_PM_RESET_SATA = 1016,
190 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
191 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
192 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
193 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
194 ZYNQMP_PM_RESET_APU_L2 = 1021,
195 ZYNQMP_PM_RESET_ACPU3 = 1022,
196 ZYNQMP_PM_RESET_ACPU2 = 1023,
197 ZYNQMP_PM_RESET_ACPU1 = 1024,
198 ZYNQMP_PM_RESET_ACPU0 = 1025,
199 ZYNQMP_PM_RESET_DDR = 1026,
200 ZYNQMP_PM_RESET_APM_FPD = 1027,
201 ZYNQMP_PM_RESET_SOFT = 1028,
202 ZYNQMP_PM_RESET_GEM0 = 1029,
203 ZYNQMP_PM_RESET_GEM1 = 1030,
204 ZYNQMP_PM_RESET_GEM2 = 1031,
205 ZYNQMP_PM_RESET_GEM3 = 1032,
206 ZYNQMP_PM_RESET_QSPI = 1033,
207 ZYNQMP_PM_RESET_UART0 = 1034,
208 ZYNQMP_PM_RESET_UART1 = 1035,
209 ZYNQMP_PM_RESET_SPI0 = 1036,
210 ZYNQMP_PM_RESET_SPI1 = 1037,
211 ZYNQMP_PM_RESET_SDIO0 = 1038,
212 ZYNQMP_PM_RESET_SDIO1 = 1039,
213 ZYNQMP_PM_RESET_CAN0 = 1040,
214 ZYNQMP_PM_RESET_CAN1 = 1041,
215 ZYNQMP_PM_RESET_I2C0 = 1042,
216 ZYNQMP_PM_RESET_I2C1 = 1043,
217 ZYNQMP_PM_RESET_TTC0 = 1044,
218 ZYNQMP_PM_RESET_TTC1 = 1045,
219 ZYNQMP_PM_RESET_TTC2 = 1046,
220 ZYNQMP_PM_RESET_TTC3 = 1047,
221 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
222 ZYNQMP_PM_RESET_NAND = 1049,
223 ZYNQMP_PM_RESET_ADMA = 1050,
224 ZYNQMP_PM_RESET_GPIO = 1051,
225 ZYNQMP_PM_RESET_IOU_CC = 1052,
226 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
227 ZYNQMP_PM_RESET_RPU_R50 = 1054,
228 ZYNQMP_PM_RESET_RPU_R51 = 1055,
229 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
230 ZYNQMP_PM_RESET_OCM = 1057,
231 ZYNQMP_PM_RESET_RPU_PGE = 1058,
232 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
233 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
234 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
235 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
236 ZYNQMP_PM_RESET_USB0_APB = 1063,
237 ZYNQMP_PM_RESET_USB1_APB = 1064,
238 ZYNQMP_PM_RESET_IPI = 1065,
239 ZYNQMP_PM_RESET_APM_LPD = 1066,
240 ZYNQMP_PM_RESET_RTC = 1067,
241 ZYNQMP_PM_RESET_SYSMON = 1068,
242 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
243 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
244 ZYNQMP_PM_RESET_FPD = 1071,
245 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
246 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
247 ZYNQMP_PM_RESET_DBG_LPD = 1074,
248 ZYNQMP_PM_RESET_DBG_FPD = 1075,
249 ZYNQMP_PM_RESET_APLL = 1076,
250 ZYNQMP_PM_RESET_DPLL = 1077,
251 ZYNQMP_PM_RESET_VPLL = 1078,
252 ZYNQMP_PM_RESET_IOPLL = 1079,
253 ZYNQMP_PM_RESET_RPLL = 1080,
254 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
255 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
256 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
257 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
258 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
259 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
260 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
261 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
262 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
263 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
264 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
265 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
266 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
267 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
268 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
269 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
270 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
271 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
272 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
273 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
274 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
275 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
276 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
277 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
278 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
279 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
280 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
281 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
282 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
283 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
284 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
285 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
286 ZYNQMP_PM_RESET_RPU_LS = 1113,
287 ZYNQMP_PM_RESET_PS_ONLY = 1114,
288 ZYNQMP_PM_RESET_PL = 1115,
289 ZYNQMP_PM_RESET_PS_PL0 = 1116,
290 ZYNQMP_PM_RESET_PS_PL1 = 1117,
291 ZYNQMP_PM_RESET_PS_PL2 = 1118,
292 ZYNQMP_PM_RESET_PS_PL3 = 1119,
293 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
294};
295
296enum zynqmp_pm_suspend_reason {
297 SUSPEND_POWER_REQUEST = 201,
298 SUSPEND_ALERT = 202,
299 SUSPEND_SYSTEM_SHUTDOWN = 203,
300};
301
302enum zynqmp_pm_request_ack {
303 ZYNQMP_PM_REQUEST_ACK_NO = 1,
304 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
305 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
306};
307
308enum pm_node_id {
309 NODE_SD_0 = 39,
310 NODE_SD_1 = 40,
311};
312
313enum tap_delay_type {
314 PM_TAPDELAY_INPUT = 0,
315 PM_TAPDELAY_OUTPUT = 1,
316};
317
318enum dll_reset_type {
319 PM_DLL_RESET_ASSERT = 0,
320 PM_DLL_RESET_RELEASE = 1,
321 PM_DLL_RESET_PULSE = 2,
322};
323
324enum pm_pinctrl_config_param {
325 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
326 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
327 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
328 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
329 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
330 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
331 PM_PINCTRL_CONFIG_TRI_STATE = 6,
332 PM_PINCTRL_CONFIG_MAX = 7,
333};
334
335enum pm_pinctrl_slew_rate {
336 PM_PINCTRL_SLEW_RATE_FAST = 0,
337 PM_PINCTRL_SLEW_RATE_SLOW = 1,
338};
339
340enum pm_pinctrl_bias_status {
341 PM_PINCTRL_BIAS_DISABLE = 0,
342 PM_PINCTRL_BIAS_ENABLE = 1,
343};
344
345enum pm_pinctrl_pull_ctrl {
346 PM_PINCTRL_BIAS_PULL_DOWN = 0,
347 PM_PINCTRL_BIAS_PULL_UP = 1,
348};
349
350enum pm_pinctrl_schmitt_cmos {
351 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
352 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
353};
354
355enum pm_pinctrl_drive_strength {
356 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
357 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
358 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
359 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
360};
361
362enum zynqmp_pm_shutdown_type {
363 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
364 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
365 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
366};
367
368enum zynqmp_pm_shutdown_subtype {
369 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
370 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
371 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
372};
373
374enum ospi_mux_select_type {
375 PM_OSPI_MUX_SEL_DMA = 0,
376 PM_OSPI_MUX_SEL_LINEAR = 1,
377};
378
379/**
380 * struct zynqmp_pm_query_data - PM query data
381 * @qid: query ID
382 * @arg1: Argument 1 of query data
383 * @arg2: Argument 2 of query data
384 * @arg3: Argument 3 of query data
385 */
386struct zynqmp_pm_query_data {
387 u32 qid;
388 u32 arg1;
389 u32 arg2;
390 u32 arg3;
391};
392
393int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
394 u32 arg2, u32 arg3, u32 *ret_payload);
395
396#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
397int zynqmp_pm_get_api_version(u32 *version);
398int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
399int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
400int zynqmp_pm_clock_enable(u32 clock_id);
401int zynqmp_pm_clock_disable(u32 clock_id);
402int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
403int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
404int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
405int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
406int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
407int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
408int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
409int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
410int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
411int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
412int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
413int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
414int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
415int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
416int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
417 const enum zynqmp_pm_reset_action assert_flag);
418int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
419unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
420int zynqmp_pm_bootmode_write(u32 ps_mode);
421int zynqmp_pm_init_finalize(void);
422int zynqmp_pm_set_suspend_mode(u32 mode);
423int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
424 const u32 qos, const enum zynqmp_pm_request_ack ack);
425int zynqmp_pm_release_node(const u32 node);
426int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
427 const u32 qos,
428 const enum zynqmp_pm_request_ack ack);
429int zynqmp_pm_aes_engine(const u64 address, u32 *out);
430int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
431int zynqmp_pm_fpga_get_status(u32 *value);
432int zynqmp_pm_write_ggs(u32 index, u32 value);
433int zynqmp_pm_read_ggs(u32 index, u32 *value);
434int zynqmp_pm_write_pggs(u32 index, u32 value);
435int zynqmp_pm_read_pggs(u32 index, u32 *value);
436int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
437int zynqmp_pm_set_boot_health_status(u32 value);
438int zynqmp_pm_pinctrl_request(const u32 pin);
439int zynqmp_pm_pinctrl_release(const u32 pin);
440int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
441int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
442int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
443 u32 *value);
444int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
445 u32 value);
446int zynqmp_pm_load_pdi(const u32 src, const u64 address);
447int zynqmp_pm_register_notifier(const u32 node, const u32 event,
448 const u32 wake, const u32 enable);
449int zynqmp_pm_feature(const u32 api_id);
450#else
451static inline int zynqmp_pm_get_api_version(u32 *version)
452{
453 return -ENODEV;
454}
455
456static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
457{
458 return -ENODEV;
459}
460
461static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
462 u32 *out)
463{
464 return -ENODEV;
465}
466
467static inline int zynqmp_pm_clock_enable(u32 clock_id)
468{
469 return -ENODEV;
470}
471
472static inline int zynqmp_pm_clock_disable(u32 clock_id)
473{
474 return -ENODEV;
475}
476
477static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
478{
479 return -ENODEV;
480}
481
482static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
483{
484 return -ENODEV;
485}
486
487static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
488{
489 return -ENODEV;
490}
491
492static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
493{
494 return -ENODEV;
495}
496
497static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
498{
499 return -ENODEV;
500}
501
502static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
503{
504 return -ENODEV;
505}
506
507static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
508{
509 return -ENODEV;
510}
511
512static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
513{
514 return -ENODEV;
515}
516
517static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
518{
519 return -ENODEV;
520}
521
522static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
523{
524 return -ENODEV;
525}
526
527static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
528{
529 return -ENODEV;
530}
531
532static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
533{
534 return -ENODEV;
535}
536
537static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
538{
539 return -ENODEV;
540}
541
542static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
543{
544 return -ENODEV;
545}
546
547static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
548 const enum zynqmp_pm_reset_action assert_flag)
549{
550 return -ENODEV;
551}
552
553static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
554 u32 *status)
555{
556 return -ENODEV;
557}
558
559static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
560{
561 return -ENODEV;
562}
563
564static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
565{
566 return -ENODEV;
567}
568
569static inline int zynqmp_pm_init_finalize(void)
570{
571 return -ENODEV;
572}
573
574static inline int zynqmp_pm_set_suspend_mode(u32 mode)
575{
576 return -ENODEV;
577}
578
579static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
580 const u32 qos,
581 const enum zynqmp_pm_request_ack ack)
582{
583 return -ENODEV;
584}
585
586static inline int zynqmp_pm_release_node(const u32 node)
587{
588 return -ENODEV;
589}
590
591static inline int zynqmp_pm_set_requirement(const u32 node,
592 const u32 capabilities,
593 const u32 qos,
594 const enum zynqmp_pm_request_ack ack)
595{
596 return -ENODEV;
597}
598
599static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
600{
601 return -ENODEV;
602}
603
604static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
605 const u32 flags)
606{
607 return -ENODEV;
608}
609
610static inline int zynqmp_pm_fpga_get_status(u32 *value)
611{
612 return -ENODEV;
613}
614
615static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
616{
617 return -ENODEV;
618}
619
620static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
621{
622 return -ENODEV;
623}
624
625static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
626{
627 return -ENODEV;
628}
629
630static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
631{
632 return -ENODEV;
633}
634
635static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
636{
637 return -ENODEV;
638}
639
640static inline int zynqmp_pm_set_boot_health_status(u32 value)
641{
642 return -ENODEV;
643}
644
645static inline int zynqmp_pm_pinctrl_request(const u32 pin)
646{
647 return -ENODEV;
648}
649
650static inline int zynqmp_pm_pinctrl_release(const u32 pin)
651{
652 return -ENODEV;
653}
654
655static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
656{
657 return -ENODEV;
658}
659
660static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
661{
662 return -ENODEV;
663}
664
665static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
666 u32 *value)
667{
668 return -ENODEV;
669}
670
671static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
672 u32 value)
673{
674 return -ENODEV;
675}
676
677static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
678{
679 return -ENODEV;
680}
681
682static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
683 const u32 wake, const u32 enable)
684{
685 return -ENODEV;
686}
687
688static inline int zynqmp_pm_feature(const u32 api_id)
689{
690 return -ENODEV;
691}
692#endif
693
694#endif /* __FIRMWARE_ZYNQMP_H__ */