tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright 2019 IBM Corp.
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6#include <dt-bindings/clock/ast2600-clock.h>
7
8/ {
9 model = "Aspeed BMC";
10 compatible = "aspeed,ast2600";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
14
15 aliases {
16 i2c0 = &i2c0;
17 i2c1 = &i2c1;
18 i2c2 = &i2c2;
19 i2c3 = &i2c3;
20 i2c4 = &i2c4;
21 i2c5 = &i2c5;
22 i2c6 = &i2c6;
23 i2c7 = &i2c7;
24 i2c8 = &i2c8;
25 i2c9 = &i2c9;
26 i2c10 = &i2c10;
27 i2c11 = &i2c11;
28 i2c12 = &i2c12;
29 i2c13 = &i2c13;
30 i2c14 = &i2c14;
31 i2c15 = &i2c15;
32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 serial3 = &uart4;
36 serial4 = &uart5;
37 serial5 = &vuart1;
38 serial6 = &vuart2;
39 };
40
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "aspeed,ast2600-smp";
46
47 cpu@f00 {
48 compatible = "arm,cortex-a7";
49 device_type = "cpu";
50 reg = <0xf00>;
51 };
52
53 cpu@f01 {
54 compatible = "arm,cortex-a7";
55 device_type = "cpu";
56 reg = <0xf01>;
57 };
58 };
59
60 timer {
61 compatible = "arm,armv7-timer";
62 interrupt-parent = <&gic>;
63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
67 clocks = <&syscon ASPEED_CLK_HPLL>;
68 arm,cpu-registers-not-fw-configured;
69 always-on;
70 };
71
72 edac: sdram@1e6e0000 {
73 compatible = "aspeed,ast2600-sdram-edac", "syscon";
74 reg = <0x1e6e0000 0x174>;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
76 };
77
78 ahb {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 device_type = "soc";
83 ranges;
84
85 gic: interrupt-controller@40461000 {
86 compatible = "arm,cortex-a7-gic";
87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
88 #interrupt-cells = <3>;
89 interrupt-controller;
90 interrupt-parent = <&gic>;
91 reg = <0x40461000 0x1000>,
92 <0x40462000 0x1000>,
93 <0x40464000 0x2000>,
94 <0x40466000 0x2000>;
95 };
96
97 fmc: spi@1e620000 {
98 reg = < 0x1e620000 0xc4
99 0x20000000 0x10000000 >;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 compatible = "aspeed,ast2600-fmc";
103 clocks = <&syscon ASPEED_CLK_AHB>;
104 status = "disabled";
105 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
106 flash@0 {
107 reg = < 0 >;
108 compatible = "jedec,spi-nor";
109 spi-max-frequency = <50000000>;
110 status = "disabled";
111 };
112 flash@1 {
113 reg = < 1 >;
114 compatible = "jedec,spi-nor";
115 spi-max-frequency = <50000000>;
116 status = "disabled";
117 };
118 flash@2 {
119 reg = < 2 >;
120 compatible = "jedec,spi-nor";
121 spi-max-frequency = <50000000>;
122 status = "disabled";
123 };
124 };
125
126 spi1: spi@1e630000 {
127 reg = < 0x1e630000 0xc4
128 0x30000000 0x10000000 >;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "aspeed,ast2600-spi";
132 clocks = <&syscon ASPEED_CLK_AHB>;
133 status = "disabled";
134 flash@0 {
135 reg = < 0 >;
136 compatible = "jedec,spi-nor";
137 spi-max-frequency = <50000000>;
138 status = "disabled";
139 };
140 flash@1 {
141 reg = < 1 >;
142 compatible = "jedec,spi-nor";
143 spi-max-frequency = <50000000>;
144 status = "disabled";
145 };
146 };
147
148 spi2: spi@1e631000 {
149 reg = < 0x1e631000 0xc4
150 0x50000000 0x10000000 >;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "aspeed,ast2600-spi";
154 clocks = <&syscon ASPEED_CLK_AHB>;
155 status = "disabled";
156 flash@0 {
157 reg = < 0 >;
158 compatible = "jedec,spi-nor";
159 spi-max-frequency = <50000000>;
160 status = "disabled";
161 };
162 flash@1 {
163 reg = < 1 >;
164 compatible = "jedec,spi-nor";
165 spi-max-frequency = <50000000>;
166 status = "disabled";
167 };
168 flash@2 {
169 reg = < 2 >;
170 compatible = "jedec,spi-nor";
171 spi-max-frequency = <50000000>;
172 status = "disabled";
173 };
174 };
175
176 mdio0: mdio@1e650000 {
177 compatible = "aspeed,ast2600-mdio";
178 reg = <0x1e650000 0x8>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_mdio1_default>;
184 };
185
186 mdio1: mdio@1e650008 {
187 compatible = "aspeed,ast2600-mdio";
188 reg = <0x1e650008 0x8>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 status = "disabled";
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_mdio2_default>;
194 };
195
196 mdio2: mdio@1e650010 {
197 compatible = "aspeed,ast2600-mdio";
198 reg = <0x1e650010 0x8>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 status = "disabled";
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_mdio3_default>;
204 };
205
206 mdio3: mdio@1e650018 {
207 compatible = "aspeed,ast2600-mdio";
208 reg = <0x1e650018 0x8>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 status = "disabled";
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_mdio4_default>;
214 };
215
216 mac0: ftgmac@1e660000 {
217 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
218 reg = <0x1e660000 0x180>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
223 status = "disabled";
224 };
225
226 mac1: ftgmac@1e680000 {
227 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
228 reg = <0x1e680000 0x180>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
233 status = "disabled";
234 };
235
236 mac2: ftgmac@1e670000 {
237 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
238 reg = <0x1e670000 0x180>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
243 status = "disabled";
244 };
245
246 mac3: ftgmac@1e690000 {
247 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
248 reg = <0x1e690000 0x180>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
253 status = "disabled";
254 };
255
256 ehci0: usb@1e6a1000 {
257 compatible = "aspeed,ast2600-ehci", "generic-ehci";
258 reg = <0x1e6a1000 0x100>;
259 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_usb2ah_default>;
263 status = "disabled";
264 };
265
266 ehci1: usb@1e6a3000 {
267 compatible = "aspeed,ast2600-ehci", "generic-ehci";
268 reg = <0x1e6a3000 0x100>;
269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_usb2bh_default>;
273 status = "disabled";
274 };
275
276 uhci: usb@1e6b0000 {
277 compatible = "aspeed,ast2600-uhci", "generic-uhci";
278 reg = <0x1e6b0000 0x100>;
279 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
280 #ports = <2>;
281 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
282 status = "disabled";
283 /*
284 * No default pinmux, it will follow EHCI, use an
285 * explicit pinmux override if EHCI is not enabled.
286 */
287 };
288
289 vhub: usb-vhub@1e6a0000 {
290 compatible = "aspeed,ast2600-usb-vhub";
291 reg = <0x1e6a0000 0x350>;
292 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
294 aspeed,vhub-downstream-ports = <7>;
295 aspeed,vhub-generic-endpoints = <21>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_usb2ad_default>;
298 status = "disabled";
299 };
300
301 apb {
302 compatible = "simple-bus";
303 #address-cells = <1>;
304 #size-cells = <1>;
305 ranges;
306
307 syscon: syscon@1e6e2000 {
308 compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
309 reg = <0x1e6e2000 0x1000>;
310 ranges = <0 0x1e6e2000 0x1000>;
311 #address-cells = <1>;
312 #size-cells = <1>;
313 #clock-cells = <1>;
314 #reset-cells = <1>;
315
316 pinctrl: pinctrl {
317 compatible = "aspeed,ast2600-pinctrl";
318 };
319
320 silicon-id@14 {
321 compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id";
322 reg = <0x14 0x4 0x5b0 0x8>;
323 };
324
325 smp-memram@180 {
326 compatible = "aspeed,ast2600-smpmem";
327 reg = <0x180 0x40>;
328 };
329
330 scu_ic0: interrupt-controller@560 {
331 #interrupt-cells = <1>;
332 compatible = "aspeed,ast2600-scu-ic0";
333 reg = <0x560 0x4>;
334 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-controller;
336 };
337
338 scu_ic1: interrupt-controller@570 {
339 #interrupt-cells = <1>;
340 compatible = "aspeed,ast2600-scu-ic1";
341 reg = <0x570 0x4>;
342 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-controller;
344 };
345 };
346
347 rng: hwrng@1e6e2524 {
348 compatible = "timeriomem_rng";
349 reg = <0x1e6e2524 0x4>;
350 period = <1>;
351 quality = <100>;
352 };
353
354 xdma: xdma@1e6e7000 {
355 compatible = "aspeed,ast2600-xdma";
356 reg = <0x1e6e7000 0x100>;
357 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
358 resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
359 reset-names = "device", "root-complex";
360 interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
361 <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
362 aspeed,pcie-device = "bmc";
363 aspeed,scu = <&syscon>;
364 status = "disabled";
365 };
366
367 adc0: adc@1e6e9000 {
368 compatible = "aspeed,ast2600-adc0";
369 reg = <0x1e6e9000 0x100>;
370 clocks = <&syscon ASPEED_CLK_APB2>;
371 resets = <&syscon ASPEED_RESET_ADC>;
372 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
373 #io-channel-cells = <1>;
374 status = "disabled";
375 };
376
377 adc1: adc@1e6e9100 {
378 compatible = "aspeed,ast2600-adc1";
379 reg = <0x1e6e9100 0x100>;
380 clocks = <&syscon ASPEED_CLK_APB2>;
381 resets = <&syscon ASPEED_RESET_ADC>;
382 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
383 #io-channel-cells = <1>;
384 status = "disabled";
385 };
386
387 sbc: secure-boot-controller@1e6f2000 {
388 compatible = "aspeed,ast2600-sbc";
389 reg = <0x1e6f2000 0x1000>;
390 };
391
392 gpio0: gpio@1e780000 {
393 #gpio-cells = <2>;
394 gpio-controller;
395 compatible = "aspeed,ast2600-gpio";
396 reg = <0x1e780000 0x400>;
397 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
398 gpio-ranges = <&pinctrl 0 0 208>;
399 ngpios = <208>;
400 clocks = <&syscon ASPEED_CLK_APB2>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 };
404
405 sgpiom0: sgpiom@1e780500 {
406 #gpio-cells = <2>;
407 gpio-controller;
408 compatible = "aspeed,ast2600-sgpiom";
409 reg = <0x1e780500 0x100>;
410 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&syscon ASPEED_CLK_APB2>;
412 interrupt-controller;
413 bus-frequency = <12000000>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_sgpm1_default>;
416 status = "disabled";
417 };
418
419 sgpiom1: sgpiom@1e780600 {
420 #gpio-cells = <2>;
421 gpio-controller;
422 compatible = "aspeed,ast2600-sgpiom";
423 reg = <0x1e780600 0x100>;
424 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&syscon ASPEED_CLK_APB2>;
426 interrupt-controller;
427 bus-frequency = <12000000>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_sgpm2_default>;
430 status = "disabled";
431 };
432
433 gpio1: gpio@1e780800 {
434 #gpio-cells = <2>;
435 gpio-controller;
436 compatible = "aspeed,ast2600-gpio";
437 reg = <0x1e780800 0x800>;
438 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 gpio-ranges = <&pinctrl 0 208 36>;
440 ngpios = <36>;
441 clocks = <&syscon ASPEED_CLK_APB1>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 };
445
446 rtc: rtc@1e781000 {
447 compatible = "aspeed,ast2600-rtc";
448 reg = <0x1e781000 0x18>;
449 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
450 status = "disabled";
451 };
452
453 timer: timer@1e782000 {
454 compatible = "aspeed,ast2600-timer";
455 reg = <0x1e782000 0x90>;
456 interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
457 <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
458 <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
459 <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
460 <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
461 <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
462 <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
463 <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&syscon ASPEED_CLK_APB1>;
465 clock-names = "PCLK";
466 status = "disabled";
467 };
468
469 uart1: serial@1e783000 {
470 compatible = "ns16550a";
471 reg = <0x1e783000 0x20>;
472 reg-shift = <2>;
473 reg-io-width = <4>;
474 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
476 resets = <&lpc_reset 4>;
477 no-loopback-test;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
480 status = "disabled";
481 };
482
483 uart5: serial@1e784000 {
484 compatible = "ns16550a";
485 reg = <0x1e784000 0x1000>;
486 reg-shift = <2>;
487 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
489 no-loopback-test;
490 };
491
492 wdt1: watchdog@1e785000 {
493 compatible = "aspeed,ast2600-wdt";
494 reg = <0x1e785000 0x40>;
495 };
496
497 wdt2: watchdog@1e785040 {
498 compatible = "aspeed,ast2600-wdt";
499 reg = <0x1e785040 0x40>;
500 status = "disabled";
501 };
502
503 wdt3: watchdog@1e785080 {
504 compatible = "aspeed,ast2600-wdt";
505 reg = <0x1e785080 0x40>;
506 status = "disabled";
507 };
508
509 wdt4: watchdog@1e7850c0 {
510 compatible = "aspeed,ast2600-wdt";
511 reg = <0x1e7850C0 0x40>;
512 status = "disabled";
513 };
514
515 lpc: lpc@1e789000 {
516 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
517 reg = <0x1e789000 0x1000>;
518 reg-io-width = <4>;
519
520 #address-cells = <1>;
521 #size-cells = <1>;
522 ranges = <0x0 0x1e789000 0x1000>;
523
524 kcs1: kcs@24 {
525 compatible = "aspeed,ast2500-kcs-bmc-v2";
526 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
527 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
529 kcs_chan = <1>;
530 status = "disabled";
531 };
532
533 kcs2: kcs@28 {
534 compatible = "aspeed,ast2500-kcs-bmc-v2";
535 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
536 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
538 status = "disabled";
539 };
540
541 kcs3: kcs@2c {
542 compatible = "aspeed,ast2500-kcs-bmc-v2";
543 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
544 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
546 status = "disabled";
547 };
548
549 kcs4: kcs@114 {
550 compatible = "aspeed,ast2500-kcs-bmc-v2";
551 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
552 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
554 status = "disabled";
555 };
556
557 lpc_ctrl: lpc-ctrl@80 {
558 compatible = "aspeed,ast2600-lpc-ctrl";
559 reg = <0x80 0x80>;
560 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
561 status = "disabled";
562 };
563
564 lpc_snoop: lpc-snoop@80 {
565 compatible = "aspeed,ast2600-lpc-snoop";
566 reg = <0x80 0x80>;
567 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
569 status = "disabled";
570 };
571
572 lhc: lhc@a0 {
573 compatible = "aspeed,ast2600-lhc";
574 reg = <0xa0 0x24 0xc8 0x8>;
575 };
576
577 lpc_reset: reset-controller@98 {
578 compatible = "aspeed,ast2600-lpc-reset";
579 reg = <0x98 0x4>;
580 #reset-cells = <1>;
581 };
582
583 uart_routing: uart-routing@98 {
584 compatible = "aspeed,ast2600-uart-routing";
585 reg = <0x98 0x8>;
586 status = "disabled";
587 };
588
589 ibt: ibt@140 {
590 compatible = "aspeed,ast2600-ibt-bmc";
591 reg = <0x140 0x18>;
592 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
594 status = "disabled";
595 };
596 };
597
598 sdc: sdc@1e740000 {
599 compatible = "aspeed,ast2600-sd-controller";
600 reg = <0x1e740000 0x100>;
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0 0x1e740000 0x10000>;
604 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
605 status = "disabled";
606
607 sdhci0: sdhci@1e740100 {
608 compatible = "aspeed,ast2600-sdhci", "sdhci";
609 reg = <0x100 0x100>;
610 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
611 sdhci,auto-cmd12;
612 clocks = <&syscon ASPEED_CLK_SDIO>;
613 status = "disabled";
614 };
615
616 sdhci1: sdhci@1e740200 {
617 compatible = "aspeed,ast2600-sdhci", "sdhci";
618 reg = <0x200 0x100>;
619 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
620 sdhci,auto-cmd12;
621 clocks = <&syscon ASPEED_CLK_SDIO>;
622 status = "disabled";
623 };
624 };
625
626 emmc_controller: sdc@1e750000 {
627 compatible = "aspeed,ast2600-sd-controller";
628 reg = <0x1e750000 0x100>;
629 #address-cells = <1>;
630 #size-cells = <1>;
631 ranges = <0 0x1e750000 0x10000>;
632 clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
633 status = "disabled";
634
635 emmc: sdhci@1e750100 {
636 compatible = "aspeed,ast2600-sdhci";
637 reg = <0x100 0x100>;
638 sdhci,auto-cmd12;
639 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&syscon ASPEED_CLK_EMMC>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&pinctrl_emmc_default>;
643 };
644 };
645
646 vuart1: serial@1e787000 {
647 compatible = "aspeed,ast2500-vuart";
648 reg = <0x1e787000 0x40>;
649 reg-shift = <2>;
650 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&syscon ASPEED_CLK_APB1>;
652 no-loopback-test;
653 status = "disabled";
654 };
655
656 vuart2: serial@1e788000 {
657 compatible = "aspeed,ast2500-vuart";
658 reg = <0x1e788000 0x40>;
659 reg-shift = <2>;
660 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&syscon ASPEED_CLK_APB1>;
662 no-loopback-test;
663 status = "disabled";
664 };
665
666 uart2: serial@1e78d000 {
667 compatible = "ns16550a";
668 reg = <0x1e78d000 0x20>;
669 reg-shift = <2>;
670 reg-io-width = <4>;
671 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
673 resets = <&lpc_reset 5>;
674 no-loopback-test;
675 pinctrl-names = "default";
676 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
677 status = "disabled";
678 };
679
680 uart3: serial@1e78e000 {
681 compatible = "ns16550a";
682 reg = <0x1e78e000 0x20>;
683 reg-shift = <2>;
684 reg-io-width = <4>;
685 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
687 resets = <&lpc_reset 6>;
688 no-loopback-test;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
691 status = "disabled";
692 };
693
694 uart4: serial@1e78f000 {
695 compatible = "ns16550a";
696 reg = <0x1e78f000 0x20>;
697 reg-shift = <2>;
698 reg-io-width = <4>;
699 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
701 resets = <&lpc_reset 7>;
702 no-loopback-test;
703 pinctrl-names = "default";
704 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
705 status = "disabled";
706 };
707
708 i2c: bus@1e78a000 {
709 compatible = "simple-bus";
710 #address-cells = <1>;
711 #size-cells = <1>;
712 ranges = <0 0x1e78a000 0x1000>;
713 };
714
715 fsim0: fsi@1e79b000 {
716 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
717 reg = <0x1e79b000 0x94>;
718 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_fsi1_default>;
721 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
722 status = "disabled";
723 };
724
725 fsim1: fsi@1e79b100 {
726 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
727 reg = <0x1e79b100 0x94>;
728 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_fsi2_default>;
731 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
732 status = "disabled";
733 };
734 };
735 };
736};
737
738#include "aspeed-g6-pinctrl.dtsi"
739
740&i2c {
741 i2c0: i2c-bus@80 {
742 #address-cells = <1>;
743 #size-cells = <0>;
744 #interrupt-cells = <1>;
745 reg = <0x80 0x80>;
746 compatible = "aspeed,ast2600-i2c-bus";
747 clocks = <&syscon ASPEED_CLK_APB2>;
748 resets = <&syscon ASPEED_RESET_I2C>;
749 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
750 bus-frequency = <100000>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_i2c1_default>;
753 status = "disabled";
754 };
755
756 i2c1: i2c-bus@100 {
757 #address-cells = <1>;
758 #size-cells = <0>;
759 #interrupt-cells = <1>;
760 reg = <0x100 0x80>;
761 compatible = "aspeed,ast2600-i2c-bus";
762 clocks = <&syscon ASPEED_CLK_APB2>;
763 resets = <&syscon ASPEED_RESET_I2C>;
764 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
765 bus-frequency = <100000>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_i2c2_default>;
768 status = "disabled";
769 };
770
771 i2c2: i2c-bus@180 {
772 #address-cells = <1>;
773 #size-cells = <0>;
774 #interrupt-cells = <1>;
775 reg = <0x180 0x80>;
776 compatible = "aspeed,ast2600-i2c-bus";
777 clocks = <&syscon ASPEED_CLK_APB2>;
778 resets = <&syscon ASPEED_RESET_I2C>;
779 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
780 bus-frequency = <100000>;
781 pinctrl-names = "default";
782 pinctrl-0 = <&pinctrl_i2c3_default>;
783 status = "disabled";
784 };
785
786 i2c3: i2c-bus@200 {
787 #address-cells = <1>;
788 #size-cells = <0>;
789 #interrupt-cells = <1>;
790 reg = <0x200 0x80>;
791 compatible = "aspeed,ast2600-i2c-bus";
792 clocks = <&syscon ASPEED_CLK_APB2>;
793 resets = <&syscon ASPEED_RESET_I2C>;
794 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
795 bus-frequency = <100000>;
796 pinctrl-names = "default";
797 pinctrl-0 = <&pinctrl_i2c4_default>;
798 status = "disabled";
799 };
800
801 i2c4: i2c-bus@280 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804 #interrupt-cells = <1>;
805 reg = <0x280 0x80>;
806 compatible = "aspeed,ast2600-i2c-bus";
807 clocks = <&syscon ASPEED_CLK_APB2>;
808 resets = <&syscon ASPEED_RESET_I2C>;
809 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
810 bus-frequency = <100000>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&pinctrl_i2c5_default>;
813 status = "disabled";
814 };
815
816 i2c5: i2c-bus@300 {
817 #address-cells = <1>;
818 #size-cells = <0>;
819 #interrupt-cells = <1>;
820 reg = <0x300 0x80>;
821 compatible = "aspeed,ast2600-i2c-bus";
822 clocks = <&syscon ASPEED_CLK_APB2>;
823 resets = <&syscon ASPEED_RESET_I2C>;
824 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
825 bus-frequency = <100000>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&pinctrl_i2c6_default>;
828 status = "disabled";
829 };
830
831 i2c6: i2c-bus@380 {
832 #address-cells = <1>;
833 #size-cells = <0>;
834 #interrupt-cells = <1>;
835 reg = <0x380 0x80>;
836 compatible = "aspeed,ast2600-i2c-bus";
837 clocks = <&syscon ASPEED_CLK_APB2>;
838 resets = <&syscon ASPEED_RESET_I2C>;
839 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
840 bus-frequency = <100000>;
841 pinctrl-names = "default";
842 pinctrl-0 = <&pinctrl_i2c7_default>;
843 status = "disabled";
844 };
845
846 i2c7: i2c-bus@400 {
847 #address-cells = <1>;
848 #size-cells = <0>;
849 #interrupt-cells = <1>;
850 reg = <0x400 0x80>;
851 compatible = "aspeed,ast2600-i2c-bus";
852 clocks = <&syscon ASPEED_CLK_APB2>;
853 resets = <&syscon ASPEED_RESET_I2C>;
854 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
855 bus-frequency = <100000>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&pinctrl_i2c8_default>;
858 status = "disabled";
859 };
860
861 i2c8: i2c-bus@480 {
862 #address-cells = <1>;
863 #size-cells = <0>;
864 #interrupt-cells = <1>;
865 reg = <0x480 0x80>;
866 compatible = "aspeed,ast2600-i2c-bus";
867 clocks = <&syscon ASPEED_CLK_APB2>;
868 resets = <&syscon ASPEED_RESET_I2C>;
869 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
870 bus-frequency = <100000>;
871 pinctrl-names = "default";
872 pinctrl-0 = <&pinctrl_i2c9_default>;
873 status = "disabled";
874 };
875
876 i2c9: i2c-bus@500 {
877 #address-cells = <1>;
878 #size-cells = <0>;
879 #interrupt-cells = <1>;
880 reg = <0x500 0x80>;
881 compatible = "aspeed,ast2600-i2c-bus";
882 clocks = <&syscon ASPEED_CLK_APB2>;
883 resets = <&syscon ASPEED_RESET_I2C>;
884 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885 bus-frequency = <100000>;
886 pinctrl-names = "default";
887 pinctrl-0 = <&pinctrl_i2c10_default>;
888 status = "disabled";
889 };
890
891 i2c10: i2c-bus@580 {
892 #address-cells = <1>;
893 #size-cells = <0>;
894 #interrupt-cells = <1>;
895 reg = <0x580 0x80>;
896 compatible = "aspeed,ast2600-i2c-bus";
897 clocks = <&syscon ASPEED_CLK_APB2>;
898 resets = <&syscon ASPEED_RESET_I2C>;
899 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
900 bus-frequency = <100000>;
901 pinctrl-names = "default";
902 pinctrl-0 = <&pinctrl_i2c11_default>;
903 status = "disabled";
904 };
905
906 i2c11: i2c-bus@600 {
907 #address-cells = <1>;
908 #size-cells = <0>;
909 #interrupt-cells = <1>;
910 reg = <0x600 0x80>;
911 compatible = "aspeed,ast2600-i2c-bus";
912 clocks = <&syscon ASPEED_CLK_APB2>;
913 resets = <&syscon ASPEED_RESET_I2C>;
914 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
915 bus-frequency = <100000>;
916 pinctrl-names = "default";
917 pinctrl-0 = <&pinctrl_i2c12_default>;
918 status = "disabled";
919 };
920
921 i2c12: i2c-bus@680 {
922 #address-cells = <1>;
923 #size-cells = <0>;
924 #interrupt-cells = <1>;
925 reg = <0x680 0x80>;
926 compatible = "aspeed,ast2600-i2c-bus";
927 clocks = <&syscon ASPEED_CLK_APB2>;
928 resets = <&syscon ASPEED_RESET_I2C>;
929 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
930 bus-frequency = <100000>;
931 pinctrl-names = "default";
932 pinctrl-0 = <&pinctrl_i2c13_default>;
933 status = "disabled";
934 };
935
936 i2c13: i2c-bus@700 {
937 #address-cells = <1>;
938 #size-cells = <0>;
939 #interrupt-cells = <1>;
940 reg = <0x700 0x80>;
941 compatible = "aspeed,ast2600-i2c-bus";
942 clocks = <&syscon ASPEED_CLK_APB2>;
943 resets = <&syscon ASPEED_RESET_I2C>;
944 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
945 bus-frequency = <100000>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&pinctrl_i2c14_default>;
948 status = "disabled";
949 };
950
951 i2c14: i2c-bus@780 {
952 #address-cells = <1>;
953 #size-cells = <0>;
954 #interrupt-cells = <1>;
955 reg = <0x780 0x80>;
956 compatible = "aspeed,ast2600-i2c-bus";
957 clocks = <&syscon ASPEED_CLK_APB2>;
958 resets = <&syscon ASPEED_RESET_I2C>;
959 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
960 bus-frequency = <100000>;
961 pinctrl-names = "default";
962 pinctrl-0 = <&pinctrl_i2c15_default>;
963 status = "disabled";
964 };
965
966 i2c15: i2c-bus@800 {
967 #address-cells = <1>;
968 #size-cells = <0>;
969 #interrupt-cells = <1>;
970 reg = <0x800 0x80>;
971 compatible = "aspeed,ast2600-i2c-bus";
972 clocks = <&syscon ASPEED_CLK_APB2>;
973 resets = <&syscon ASPEED_RESET_I2C>;
974 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
975 bus-frequency = <100000>;
976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_i2c16_default>;
978 status = "disabled";
979 };
980};