tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Intel ComboPhy Subsystem
8
9maintainers:
10 - Dilip Kota <eswara.kota@linux.intel.com>
11
12description: |
13 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
14 controllers. A single Combophy provides two PHY instances.
15
16properties:
17 $nodename:
18 pattern: "combophy(@.*|-[0-9a-f])*$"
19
20 compatible:
21 items:
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
24
25 clocks:
26 maxItems: 1
27
28 reg:
29 items:
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
32
33 reg-names:
34 items:
35 - const: core
36 - const: app
37
38 resets:
39 maxItems: 4
40
41 reset-names:
42 items:
43 - const: phy
44 - const: core
45 - const: iphy0
46 - const: iphy1
47
48 intel,syscfg:
49 $ref: /schemas/types.yaml#/definitions/phandle-array
50 description: Chip configuration registers handle and ComboPhy instance id
51
52 intel,hsio:
53 $ref: /schemas/types.yaml#/definitions/phandle-array
54 description: HSIO registers handle and ComboPhy instance id on NOC
55
56 intel,aggregation:
57 type: boolean
58 description: |
59 Specify the flag to configure ComboPHY in dual lane mode.
60
61 intel,phy-mode:
62 $ref: /schemas/types.yaml#/definitions/uint32
63 description: |
64 Mode of the two phys in ComboPhy.
65 See dt-bindings/phy/phy.h for values.
66
67 "#phy-cells":
68 const: 1
69
70required:
71 - compatible
72 - clocks
73 - reg
74 - reg-names
75 - intel,syscfg
76 - intel,hsio
77 - intel,phy-mode
78 - "#phy-cells"
79
80additionalProperties: false
81
82examples:
83 - |
84 #include <dt-bindings/phy/phy.h>
85 combophy@d0a00000 {
86 compatible = "intel,combophy-lgm", "intel,combo-phy";
87 clocks = <&cgu0 1>;
88 #phy-cells = <1>;
89 reg = <0xd0a00000 0x40000>,
90 <0xd0a40000 0x1000>;
91 reg-names = "core", "app";
92 resets = <&rcu0 0x50 6>,
93 <&rcu0 0x50 17>,
94 <&rcu0 0x50 23>,
95 <&rcu0 0x50 24>;
96 reset-names = "phy", "core", "iphy0", "iphy1";
97 intel,syscfg = <&sysconf 0>;
98 intel,hsio = <&hsiol 0>;
99 intel,phy-mode = <PHY_TYPE_PCIE>;
100 intel,aggregation;
101 };