tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L ASoC Sound Serial Interface (SSIF-2)
8
9maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11
12properties:
13 compatible:
14 items:
15 - enum:
16 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
17 - const: renesas,rz-ssi
18
19 reg:
20 maxItems: 1
21
22 interrupts:
23 maxItems: 4
24
25 interrupt-names:
26 items:
27 - const: int_req
28 - const: dma_rx
29 - const: dma_tx
30 - const: dma_rt
31
32 clocks:
33 maxItems: 4
34
35 clock-names:
36 items:
37 - const: ssi
38 - const: ssi_sfr
39 - const: audio_clk1
40 - const: audio_clk2
41
42 power-domains:
43 maxItems: 1
44
45 resets:
46 maxItems: 1
47
48 dmas:
49 minItems: 1
50 maxItems: 2
51 description:
52 The first cell represents a phandle to dmac
53 The second cell specifies the encoded MID/RID values of the SSI port
54 connected to the DMA client and the slave channel configuration
55 parameters.
56 bits[0:9] - Specifies MID/RID value of a SSI channel as below
57 MID/RID value of SSI rx0 = 0x256
58 MID/RID value of SSI tx0 = 0x255
59 MID/RID value of SSI rx1 = 0x25a
60 MID/RID value of SSI tx1 = 0x259
61 MID/RID value of SSI rt2 = 0x25f
62 MID/RID value of SSI rx3 = 0x262
63 MID/RID value of SSI tx3 = 0x261
64 bit[10] - HIEN = 1, Detects a request in response to the rising edge
65 of the signal
66 bit[11] - LVL = 0, Detects based on the edge
67 bits[12:14] - AM = 2, Bus cycle mode
68 bit[15] - TM = 0, Single transfer mode
69
70 dma-names:
71 oneOf:
72 - items:
73 - const: tx
74 - const: rx
75 - items:
76 - const: rt
77
78 '#sound-dai-cells':
79 const: 0
80
81required:
82 - compatible
83 - reg
84 - interrupts
85 - interrupt-names
86 - clocks
87 - clock-names
88 - resets
89 - '#sound-dai-cells'
90
91additionalProperties: false
92
93examples:
94 - |
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 #include <dt-bindings/clock/r9a07g044-cpg.h>
97
98 ssi0: ssi@10049c00 {
99 compatible = "renesas,r9a07g044-ssi",
100 "renesas,rz-ssi";
101 reg = <0x10049c00 0x400>;
102 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
104 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
105 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
107 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
108 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
109 <&audio_clk1>,
110 <&audio_clk2>;
111 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
112 power-domains = <&cpg>;
113 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
114 dmas = <&dmac 0x2655>,
115 <&dmac 0x2656>;
116 dma-names = "tx", "rx";
117 #sound-dai-cells = <0>;
118 };