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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_INTEL_FAMILY_H
3#define _ASM_X86_INTEL_FAMILY_H
4
5/*
6 * "Big Core" Processors (Branded as Core, Xeon, etc...)
7 *
8 * While adding a new CPUID for a new microarchitecture, add a new
9 * group to keep logically sorted out in chronological order. Within
10 * that group keep the CPUID for the variants sorted by model number.
11 *
12 * The defined symbol names have the following form:
13 * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
14 * where:
15 * OPTFAMILY Describes the family of CPUs that this belongs to. Default
16 * is assumed to be "_CORE" (and should be omitted). Other values
17 * currently in use are _ATOM and _XEON_PHI
18 * MICROARCH Is the code name for the micro-architecture for this core.
19 * N.B. Not the platform name.
20 * OPTDIFF If needed, a short string to differentiate by market segment.
21 *
22 * Common OPTDIFFs:
23 *
24 * - regular client parts
25 * _L - regular mobile parts
26 * _G - parts with extra graphics on
27 * _X - regular server parts
28 * _D - micro server parts
29 *
30 * Historical OPTDIFFs:
31 *
32 * _EP - 2 socket server parts
33 * _EX - 4+ socket server parts
34 *
35 * The #define line may optionally include a comment including platform or core
36 * names. An exception is made for skylake/kabylake where steppings seem to have gotten
37 * their own names :-(
38 */
39
40/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
41#define INTEL_FAM6_ANY X86_MODEL_ANY
42
43#define INTEL_FAM6_CORE_YONAH 0x0E
44
45#define INTEL_FAM6_CORE2_MEROM 0x0F
46#define INTEL_FAM6_CORE2_MEROM_L 0x16
47#define INTEL_FAM6_CORE2_PENRYN 0x17
48#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
49
50#define INTEL_FAM6_NEHALEM 0x1E
51#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
52#define INTEL_FAM6_NEHALEM_EP 0x1A
53#define INTEL_FAM6_NEHALEM_EX 0x2E
54
55#define INTEL_FAM6_WESTMERE 0x25
56#define INTEL_FAM6_WESTMERE_EP 0x2C
57#define INTEL_FAM6_WESTMERE_EX 0x2F
58
59#define INTEL_FAM6_SANDYBRIDGE 0x2A
60#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
61#define INTEL_FAM6_IVYBRIDGE 0x3A
62#define INTEL_FAM6_IVYBRIDGE_X 0x3E
63
64#define INTEL_FAM6_HASWELL 0x3C
65#define INTEL_FAM6_HASWELL_X 0x3F
66#define INTEL_FAM6_HASWELL_L 0x45
67#define INTEL_FAM6_HASWELL_G 0x46
68
69#define INTEL_FAM6_BROADWELL 0x3D
70#define INTEL_FAM6_BROADWELL_G 0x47
71#define INTEL_FAM6_BROADWELL_X 0x4F
72#define INTEL_FAM6_BROADWELL_D 0x56
73
74#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
75#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
76#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
77/* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
78/* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
79
80#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
81/* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
82/* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
83/* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
84
85#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
86/* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
87
88#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
89#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
90
91#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
92
93#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
94#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
95#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
96#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
97#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
98
99#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
100
101#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
102
103#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
104#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
105
106#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
107
108#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
109#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
110
111#define INTEL_FAM6_RAPTORLAKE 0xB7
112
113/* "Small Core" Processors (Atom) */
114
115#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
116#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
117
118#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
119#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
120#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
121
122#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
123#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
124#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
125
126#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
127#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
128#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
129
130#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
131#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
132
133/* Note: the micro-architecture is "Goldmont Plus" */
134#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
135
136#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
137#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
138#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
139
140/* Xeon Phi */
141
142#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
143#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
144
145/* Family 5 */
146#define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */
147
148#endif /* _ASM_X86_INTEL_FAMILY_H */