tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interconnect/qcom,msm8974.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/qcom,gcc-msm8974.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/reset/qcom,gcc-msm8974.h>
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm MSM8974";
16 compatible = "qcom,msm8974";
17 interrupt-parent = <&intc>;
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 mpss_region: mpss@8000000 {
25 reg = <0x08000000 0x5100000>;
26 no-map;
27 };
28
29 mba_region: mba@d100000 {
30 reg = <0x0d100000 0x100000>;
31 no-map;
32 };
33
34 wcnss_region: wcnss@d200000 {
35 reg = <0x0d200000 0xa00000>;
36 no-map;
37 };
38
39 adsp_region: adsp@dc00000 {
40 reg = <0x0dc00000 0x1900000>;
41 no-map;
42 };
43
44 venus@f500000 {
45 reg = <0x0f500000 0x500000>;
46 no-map;
47 };
48
49 smem_region: smem@fa00000 {
50 reg = <0xfa00000 0x200000>;
51 no-map;
52 };
53
54 tz@fc00000 {
55 reg = <0x0fc00000 0x160000>;
56 no-map;
57 };
58
59 rfsa@fd60000 {
60 reg = <0x0fd60000 0x20000>;
61 no-map;
62 };
63
64 rmtfs@fd80000 {
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0fd80000 0x180000>;
67 no-map;
68
69 qcom,client-id = <1>;
70 };
71 };
72
73 cpus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 interrupts = <GIC_PPI 9 0xf04>;
77
78 CPU0: cpu@0 {
79 compatible = "qcom,krait";
80 enable-method = "qcom,kpss-acc-v2";
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2>;
84 qcom,acc = <&acc0>;
85 qcom,saw = <&saw0>;
86 cpu-idle-states = <&CPU_SPC>;
87 };
88
89 CPU1: cpu@1 {
90 compatible = "qcom,krait";
91 enable-method = "qcom,kpss-acc-v2";
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2>;
95 qcom,acc = <&acc1>;
96 qcom,saw = <&saw1>;
97 cpu-idle-states = <&CPU_SPC>;
98 };
99
100 CPU2: cpu@2 {
101 compatible = "qcom,krait";
102 enable-method = "qcom,kpss-acc-v2";
103 device_type = "cpu";
104 reg = <2>;
105 next-level-cache = <&L2>;
106 qcom,acc = <&acc2>;
107 qcom,saw = <&saw2>;
108 cpu-idle-states = <&CPU_SPC>;
109 };
110
111 CPU3: cpu@3 {
112 compatible = "qcom,krait";
113 enable-method = "qcom,kpss-acc-v2";
114 device_type = "cpu";
115 reg = <3>;
116 next-level-cache = <&L2>;
117 qcom,acc = <&acc3>;
118 qcom,saw = <&saw3>;
119 cpu-idle-states = <&CPU_SPC>;
120 };
121
122 L2: l2-cache {
123 compatible = "cache";
124 cache-level = <2>;
125 qcom,saw = <&saw_l2>;
126 };
127
128 idle-states {
129 CPU_SPC: spc {
130 compatible = "qcom,idle-state-spc",
131 "arm,idle-state";
132 entry-latency-us = <150>;
133 exit-latency-us = <200>;
134 min-residency-us = <2000>;
135 };
136 };
137 };
138
139 memory {
140 device_type = "memory";
141 reg = <0x0 0x0>;
142 };
143
144 thermal-zones {
145 cpu0-thermal {
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
148
149 thermal-sensors = <&tsens 5>;
150
151 trips {
152 cpu_alert0: trip0 {
153 temperature = <75000>;
154 hysteresis = <2000>;
155 type = "passive";
156 };
157 cpu_crit0: trip1 {
158 temperature = <110000>;
159 hysteresis = <2000>;
160 type = "critical";
161 };
162 };
163 };
164
165 cpu1-thermal {
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
168
169 thermal-sensors = <&tsens 6>;
170
171 trips {
172 cpu_alert1: trip0 {
173 temperature = <75000>;
174 hysteresis = <2000>;
175 type = "passive";
176 };
177 cpu_crit1: trip1 {
178 temperature = <110000>;
179 hysteresis = <2000>;
180 type = "critical";
181 };
182 };
183 };
184
185 cpu2-thermal {
186 polling-delay-passive = <250>;
187 polling-delay = <1000>;
188
189 thermal-sensors = <&tsens 7>;
190
191 trips {
192 cpu_alert2: trip0 {
193 temperature = <75000>;
194 hysteresis = <2000>;
195 type = "passive";
196 };
197 cpu_crit2: trip1 {
198 temperature = <110000>;
199 hysteresis = <2000>;
200 type = "critical";
201 };
202 };
203 };
204
205 cpu3-thermal {
206 polling-delay-passive = <250>;
207 polling-delay = <1000>;
208
209 thermal-sensors = <&tsens 8>;
210
211 trips {
212 cpu_alert3: trip0 {
213 temperature = <75000>;
214 hysteresis = <2000>;
215 type = "passive";
216 };
217 cpu_crit3: trip1 {
218 temperature = <110000>;
219 hysteresis = <2000>;
220 type = "critical";
221 };
222 };
223 };
224
225 q6-dsp-thermal {
226 polling-delay-passive = <250>;
227 polling-delay = <1000>;
228
229 thermal-sensors = <&tsens 1>;
230
231 trips {
232 q6_dsp_alert0: trip-point0 {
233 temperature = <90000>;
234 hysteresis = <2000>;
235 type = "hot";
236 };
237 };
238 };
239
240 modemtx-thermal {
241 polling-delay-passive = <250>;
242 polling-delay = <1000>;
243
244 thermal-sensors = <&tsens 2>;
245
246 trips {
247 modemtx_alert0: trip-point0 {
248 temperature = <90000>;
249 hysteresis = <2000>;
250 type = "hot";
251 };
252 };
253 };
254
255 video-thermal {
256 polling-delay-passive = <250>;
257 polling-delay = <1000>;
258
259 thermal-sensors = <&tsens 3>;
260
261 trips {
262 video_alert0: trip-point0 {
263 temperature = <95000>;
264 hysteresis = <2000>;
265 type = "hot";
266 };
267 };
268 };
269
270 wlan-thermal {
271 polling-delay-passive = <250>;
272 polling-delay = <1000>;
273
274 thermal-sensors = <&tsens 4>;
275
276 trips {
277 wlan_alert0: trip-point0 {
278 temperature = <105000>;
279 hysteresis = <2000>;
280 type = "hot";
281 };
282 };
283 };
284
285 gpu-top-thermal {
286 polling-delay-passive = <250>;
287 polling-delay = <1000>;
288
289 thermal-sensors = <&tsens 9>;
290
291 trips {
292 gpu1_alert0: trip-point0 {
293 temperature = <90000>;
294 hysteresis = <2000>;
295 type = "hot";
296 };
297 };
298 };
299
300 gpu-bottom-thermal {
301 polling-delay-passive = <250>;
302 polling-delay = <1000>;
303
304 thermal-sensors = <&tsens 10>;
305
306 trips {
307 gpu2_alert0: trip-point0 {
308 temperature = <90000>;
309 hysteresis = <2000>;
310 type = "hot";
311 };
312 };
313 };
314 };
315
316 cpu-pmu {
317 compatible = "qcom,krait-pmu";
318 interrupts = <GIC_PPI 7 0xf04>;
319 };
320
321 clocks {
322 xo_board: xo_board {
323 compatible = "fixed-clock";
324 #clock-cells = <0>;
325 clock-frequency = <19200000>;
326 };
327
328 sleep_clk: sleep_clk {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <32768>;
332 };
333 };
334
335 timer {
336 compatible = "arm,armv7-timer";
337 interrupts = <GIC_PPI 2 0xf08>,
338 <GIC_PPI 3 0xf08>,
339 <GIC_PPI 4 0xf08>,
340 <GIC_PPI 1 0xf08>;
341 clock-frequency = <19200000>;
342 };
343
344 adsp-pil {
345 compatible = "qcom,msm8974-adsp-pil";
346
347 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
348 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
349 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
350 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
351 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
352 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
353
354 cx-supply = <&pm8841_s2>;
355
356 clocks = <&xo_board>;
357 clock-names = "xo";
358
359 memory-region = <&adsp_region>;
360
361 qcom,smem-states = <&adsp_smp2p_out 0>;
362 qcom,smem-state-names = "stop";
363
364 smd-edge {
365 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
366
367 qcom,ipc = <&apcs 8 8>;
368 qcom,smd-edge = <1>;
369
370 label = "lpass";
371 };
372 };
373
374 smem {
375 compatible = "qcom,smem";
376
377 memory-region = <&smem_region>;
378 qcom,rpm-msg-ram = <&rpm_msg_ram>;
379
380 hwlocks = <&tcsr_mutex 3>;
381 };
382
383 smp2p-adsp {
384 compatible = "qcom,smp2p";
385 qcom,smem = <443>, <429>;
386
387 interrupt-parent = <&intc>;
388 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
389
390 qcom,ipc = <&apcs 8 10>;
391
392 qcom,local-pid = <0>;
393 qcom,remote-pid = <2>;
394
395 adsp_smp2p_out: master-kernel {
396 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
398 };
399
400 adsp_smp2p_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
402
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406 };
407
408 smp2p-modem {
409 compatible = "qcom,smp2p";
410 qcom,smem = <435>, <428>;
411
412 interrupt-parent = <&intc>;
413 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
414
415 qcom,ipc = <&apcs 8 14>;
416
417 qcom,local-pid = <0>;
418 qcom,remote-pid = <1>;
419
420 modem_smp2p_out: master-kernel {
421 qcom,entry-name = "master-kernel";
422 #qcom,smem-state-cells = <1>;
423 };
424
425 modem_smp2p_in: slave-kernel {
426 qcom,entry-name = "slave-kernel";
427
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 };
431 };
432
433 smp2p-wcnss {
434 compatible = "qcom,smp2p";
435 qcom,smem = <451>, <431>;
436
437 interrupt-parent = <&intc>;
438 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
439
440 qcom,ipc = <&apcs 8 18>;
441
442 qcom,local-pid = <0>;
443 qcom,remote-pid = <4>;
444
445 wcnss_smp2p_out: master-kernel {
446 qcom,entry-name = "master-kernel";
447
448 #qcom,smem-state-cells = <1>;
449 };
450
451 wcnss_smp2p_in: slave-kernel {
452 qcom,entry-name = "slave-kernel";
453
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 };
457 };
458
459 smsm {
460 compatible = "qcom,smsm";
461
462 #address-cells = <1>;
463 #size-cells = <0>;
464
465 qcom,ipc-1 = <&apcs 8 13>;
466 qcom,ipc-2 = <&apcs 8 9>;
467 qcom,ipc-3 = <&apcs 8 19>;
468
469 apps_smsm: apps@0 {
470 reg = <0>;
471
472 #qcom,smem-state-cells = <1>;
473 };
474
475 modem_smsm: modem@1 {
476 reg = <1>;
477 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
478
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 };
482
483 adsp_smsm: adsp@2 {
484 reg = <2>;
485 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
486
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 };
490
491 wcnss_smsm: wcnss@7 {
492 reg = <7>;
493 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
494
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498 };
499
500 firmware {
501 scm {
502 compatible = "qcom,scm";
503 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
504 clock-names = "core", "bus", "iface";
505 };
506 };
507
508 soc: soc {
509 #address-cells = <1>;
510 #size-cells = <1>;
511 ranges;
512 compatible = "simple-bus";
513
514 intc: interrupt-controller@f9000000 {
515 compatible = "qcom,msm-qgic2";
516 interrupt-controller;
517 #interrupt-cells = <3>;
518 reg = <0xf9000000 0x1000>,
519 <0xf9002000 0x1000>;
520 };
521
522 apcs: syscon@f9011000 {
523 compatible = "syscon";
524 reg = <0xf9011000 0x1000>;
525 };
526
527 qfprom: qfprom@fc4bc000 {
528 #address-cells = <1>;
529 #size-cells = <1>;
530 compatible = "qcom,qfprom";
531 reg = <0xfc4bc000 0x1000>;
532 tsens_calib: calib@d0 {
533 reg = <0xd0 0x18>;
534 };
535 tsens_backup: backup@440 {
536 reg = <0x440 0x10>;
537 };
538 };
539
540 tsens: thermal-sensor@fc4a9000 {
541 compatible = "qcom,msm8974-tsens";
542 reg = <0xfc4a9000 0x1000>, /* TM */
543 <0xfc4a8000 0x1000>; /* SROT */
544 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
545 nvmem-cell-names = "calib", "calib_backup";
546 #qcom,sensors = <11>;
547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "uplow";
549 #thermal-sensor-cells = <1>;
550 };
551
552 timer@f9020000 {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges;
556 compatible = "arm,armv7-timer-mem";
557 reg = <0xf9020000 0x1000>;
558 clock-frequency = <19200000>;
559
560 frame@f9021000 {
561 frame-number = <0>;
562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
564 reg = <0xf9021000 0x1000>,
565 <0xf9022000 0x1000>;
566 };
567
568 frame@f9023000 {
569 frame-number = <1>;
570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
571 reg = <0xf9023000 0x1000>;
572 status = "disabled";
573 };
574
575 frame@f9024000 {
576 frame-number = <2>;
577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
578 reg = <0xf9024000 0x1000>;
579 status = "disabled";
580 };
581
582 frame@f9025000 {
583 frame-number = <3>;
584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0xf9025000 0x1000>;
586 status = "disabled";
587 };
588
589 frame@f9026000 {
590 frame-number = <4>;
591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
592 reg = <0xf9026000 0x1000>;
593 status = "disabled";
594 };
595
596 frame@f9027000 {
597 frame-number = <5>;
598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
599 reg = <0xf9027000 0x1000>;
600 status = "disabled";
601 };
602
603 frame@f9028000 {
604 frame-number = <6>;
605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
606 reg = <0xf9028000 0x1000>;
607 status = "disabled";
608 };
609 };
610
611 saw0: power-controller@f9089000 {
612 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
613 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
614 };
615
616 saw1: power-controller@f9099000 {
617 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
618 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
619 };
620
621 saw2: power-controller@f90a9000 {
622 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
623 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
624 };
625
626 saw3: power-controller@f90b9000 {
627 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
628 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
629 };
630
631 saw_l2: power-controller@f9012000 {
632 compatible = "qcom,saw2";
633 reg = <0xf9012000 0x1000>;
634 regulator;
635 };
636
637 acc0: clock-controller@f9088000 {
638 compatible = "qcom,kpss-acc-v2";
639 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
640 };
641
642 acc1: clock-controller@f9098000 {
643 compatible = "qcom,kpss-acc-v2";
644 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
645 };
646
647 acc2: clock-controller@f90a8000 {
648 compatible = "qcom,kpss-acc-v2";
649 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
650 };
651
652 acc3: clock-controller@f90b8000 {
653 compatible = "qcom,kpss-acc-v2";
654 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
655 };
656
657 restart@fc4ab000 {
658 compatible = "qcom,pshold";
659 reg = <0xfc4ab000 0x4>;
660 };
661
662 gcc: clock-controller@fc400000 {
663 compatible = "qcom,gcc-msm8974";
664 #clock-cells = <1>;
665 #reset-cells = <1>;
666 #power-domain-cells = <1>;
667 reg = <0xfc400000 0x4000>;
668 };
669
670 tcsr: syscon@fd4a0000 {
671 compatible = "syscon";
672 reg = <0xfd4a0000 0x10000>;
673 };
674
675 tcsr_mutex_block: syscon@fd484000 {
676 compatible = "syscon";
677 reg = <0xfd484000 0x2000>;
678 };
679
680 mmcc: clock-controller@fd8c0000 {
681 compatible = "qcom,mmcc-msm8974";
682 #clock-cells = <1>;
683 #reset-cells = <1>;
684 #power-domain-cells = <1>;
685 reg = <0xfd8c0000 0x6000>;
686 };
687
688 tcsr_mutex: tcsr-mutex {
689 compatible = "qcom,tcsr-mutex";
690 syscon = <&tcsr_mutex_block 0 0x80>;
691
692 #hwlock-cells = <1>;
693 };
694
695 rpm_msg_ram: memory@fc428000 {
696 compatible = "qcom,rpm-msg-ram";
697 reg = <0xfc428000 0x4000>;
698 };
699
700 blsp1_uart1: serial@f991d000 {
701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
702 reg = <0xf991d000 0x1000>;
703 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
705 clock-names = "core", "iface";
706 status = "disabled";
707 };
708
709 blsp1_uart2: serial@f991e000 {
710 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
711 reg = <0xf991e000 0x1000>;
712 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
714 clock-names = "core", "iface";
715 status = "disabled";
716 };
717
718 blsp2_uart7: serial@f995d000 {
719 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
720 reg = <0xf995d000 0x1000>;
721 interrupts = <GIC_SPI 113 IRQ_TYPE_NONE>;
722 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
723 clock-names = "core", "iface";
724 status = "disabled";
725 };
726
727 blsp2_uart8: serial@f995e000 {
728 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
729 reg = <0xf995e000 0x1000>;
730 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
732 clock-names = "core", "iface";
733 status = "disabled";
734 };
735
736 blsp2_uart10: serial@f9960000 {
737 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
738 reg = <0xf9960000 0x1000>;
739 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
741 clock-names = "core", "iface";
742 status = "disabled";
743 };
744
745 sdhci@f9824900 {
746 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
747 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
748 reg-names = "hc_mem", "core_mem";
749 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "hc_irq", "pwr_irq";
752 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
753 <&gcc GCC_SDCC1_AHB_CLK>,
754 <&xo_board>;
755 clock-names = "core", "iface", "xo";
756 status = "disabled";
757 };
758
759 sdhci@f9864900 {
760 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
761 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
762 reg-names = "hc_mem", "core_mem";
763 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-names = "hc_irq", "pwr_irq";
766 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
767 <&gcc GCC_SDCC3_AHB_CLK>,
768 <&xo_board>;
769 clock-names = "core", "iface", "xo";
770 status = "disabled";
771 };
772
773 sdhci@f98a4900 {
774 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
775 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
776 reg-names = "hc_mem", "core_mem";
777 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
779 interrupt-names = "hc_irq", "pwr_irq";
780 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
781 <&gcc GCC_SDCC2_AHB_CLK>,
782 <&xo_board>;
783 clock-names = "core", "iface", "xo";
784 status = "disabled";
785 };
786
787 otg: usb@f9a55000 {
788 compatible = "qcom,ci-hdrc";
789 reg = <0xf9a55000 0x200>,
790 <0xf9a55200 0x200>;
791 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
793 <&gcc GCC_USB_HS_SYSTEM_CLK>;
794 clock-names = "iface", "core";
795 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
796 assigned-clock-rates = <75000000>;
797 resets = <&gcc GCC_USB_HS_BCR>;
798 reset-names = "core";
799 phy_type = "ulpi";
800 dr_mode = "otg";
801 ahb-burst-config = <0>;
802 phy-names = "usb-phy";
803 status = "disabled";
804 #reset-cells = <1>;
805
806 ulpi {
807 usb_hs1_phy: phy@a {
808 compatible = "qcom,usb-hs-phy-msm8974",
809 "qcom,usb-hs-phy";
810 #phy-cells = <0>;
811 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
812 clock-names = "ref", "sleep";
813 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
814 reset-names = "phy", "por";
815 status = "disabled";
816 };
817
818 usb_hs2_phy: phy@b {
819 compatible = "qcom,usb-hs-phy-msm8974",
820 "qcom,usb-hs-phy";
821 #phy-cells = <0>;
822 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
823 clock-names = "ref", "sleep";
824 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
825 reset-names = "phy", "por";
826 status = "disabled";
827 };
828 };
829 };
830
831 rng@f9bff000 {
832 compatible = "qcom,prng";
833 reg = <0xf9bff000 0x200>;
834 clocks = <&gcc GCC_PRNG_AHB_CLK>;
835 clock-names = "core";
836 };
837
838 remoteproc@fc880000 {
839 compatible = "qcom,msm8974-mss-pil";
840 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
841 reg-names = "qdsp6", "rmb";
842
843 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
844 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
845 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
846 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
847 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
848 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
849
850 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
851 <&gcc GCC_MSS_CFG_AHB_CLK>,
852 <&gcc GCC_BOOT_ROM_AHB_CLK>,
853 <&xo_board>;
854 clock-names = "iface", "bus", "mem", "xo";
855
856 resets = <&gcc GCC_MSS_RESTART>;
857 reset-names = "mss_restart";
858
859 cx-supply = <&pm8841_s2>;
860 mss-supply = <&pm8841_s3>;
861 mx-supply = <&pm8841_s1>;
862 pll-supply = <&pm8941_l12>;
863
864 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
865
866 qcom,smem-states = <&modem_smp2p_out 0>;
867 qcom,smem-state-names = "stop";
868
869 mba {
870 memory-region = <&mba_region>;
871 };
872
873 mpss {
874 memory-region = <&mpss_region>;
875 };
876
877 smd-edge {
878 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
879
880 qcom,ipc = <&apcs 8 12>;
881 qcom,smd-edge = <0>;
882
883 label = "modem";
884 };
885 };
886
887 pronto: remoteproc@fb21b000 {
888 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
889 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
890 reg-names = "ccu", "dxe", "pmu";
891
892 memory-region = <&wcnss_region>;
893
894 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
895 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
896 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
897 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
898 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
899 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
900
901 vddpx-supply = <&pm8941_s3>;
902
903 qcom,smem-states = <&wcnss_smp2p_out 0>;
904 qcom,smem-state-names = "stop";
905
906 status = "disabled";
907
908 iris {
909 compatible = "qcom,wcn3680";
910
911 clocks = <&rpmcc RPM_SMD_CXO_A2>;
912 clock-names = "xo";
913
914 vddxo-supply = <&pm8941_l6>;
915 vddrfa-supply = <&pm8941_l11>;
916 vddpa-supply = <&pm8941_l19>;
917 vdddig-supply = <&pm8941_s3>;
918 };
919
920 smd-edge {
921 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
922
923 qcom,ipc = <&apcs 8 17>;
924 qcom,smd-edge = <6>;
925
926 wcnss {
927 compatible = "qcom,wcnss";
928 qcom,smd-channels = "WCNSS_CTRL";
929 status = "disabled";
930
931 qcom,mmio = <&pronto>;
932
933 bt {
934 compatible = "qcom,wcnss-bt";
935 };
936
937 wifi {
938 compatible = "qcom,wcnss-wlan";
939
940 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
941 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
942 interrupt-names = "tx", "rx";
943
944 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
945 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
946 };
947 };
948 };
949 };
950
951 msmgpio: pinctrl@fd510000 {
952 compatible = "qcom,msm8974-pinctrl";
953 reg = <0xfd510000 0x4000>;
954 gpio-controller;
955 gpio-ranges = <&msmgpio 0 0 146>;
956 #gpio-cells = <2>;
957 interrupt-controller;
958 #interrupt-cells = <2>;
959 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
960 };
961
962 i2c@f9923000 {
963 status = "disabled";
964 compatible = "qcom,i2c-qup-v2.1.1";
965 reg = <0xf9923000 0x1000>;
966 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
968 clock-names = "core", "iface";
969 #address-cells = <1>;
970 #size-cells = <0>;
971 };
972
973 i2c@f9924000 {
974 status = "disabled";
975 compatible = "qcom,i2c-qup-v2.1.1";
976 reg = <0xf9924000 0x1000>;
977 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
979 clock-names = "core", "iface";
980 #address-cells = <1>;
981 #size-cells = <0>;
982 };
983
984 blsp_i2c3: i2c@f9925000 {
985 status = "disabled";
986 compatible = "qcom,i2c-qup-v2.1.1";
987 reg = <0xf9925000 0x1000>;
988 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
990 clock-names = "core", "iface";
991 #address-cells = <1>;
992 #size-cells = <0>;
993 };
994
995 blsp_i2c6: i2c@f9928000 {
996 status = "disabled";
997 compatible = "qcom,i2c-qup-v2.1.1";
998 reg = <0xf9928000 0x1000>;
999 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1001 clock-names = "core", "iface";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 };
1005
1006 blsp_i2c8: i2c@f9964000 {
1007 status = "disabled";
1008 compatible = "qcom,i2c-qup-v2.1.1";
1009 reg = <0xf9964000 0x1000>;
1010 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1011 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1012 clock-names = "core", "iface";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1015 };
1016
1017 blsp_i2c11: i2c@f9967000 {
1018 status = "disabled";
1019 compatible = "qcom,i2c-qup-v2.1.1";
1020 reg = <0xf9967000 0x1000>;
1021 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1022 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1023 clock-names = "core", "iface";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
1027 dma-names = "tx", "rx";
1028 };
1029
1030 blsp_i2c12: i2c@f9968000 {
1031 status = "disabled";
1032 compatible = "qcom,i2c-qup-v2.1.1";
1033 reg = <0xf9968000 0x1000>;
1034 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1036 clock-names = "core", "iface";
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039 };
1040
1041 spmi_bus: spmi@fc4cf000 {
1042 compatible = "qcom,spmi-pmic-arb";
1043 reg-names = "core", "intr", "cnfg";
1044 reg = <0xfc4cf000 0x1000>,
1045 <0xfc4cb000 0x1000>,
1046 <0xfc4ca000 0x1000>;
1047 interrupt-names = "periph_irq";
1048 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1049 qcom,ee = <0>;
1050 qcom,channel = <0>;
1051 #address-cells = <2>;
1052 #size-cells = <0>;
1053 interrupt-controller;
1054 #interrupt-cells = <4>;
1055 };
1056
1057 blsp2_dma: dma-controller@f9944000 {
1058 compatible = "qcom,bam-v1.4.0";
1059 reg = <0xf9944000 0x19000>;
1060 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1062 clock-names = "bam_clk";
1063 #dma-cells = <1>;
1064 qcom,ee = <0>;
1065 };
1066
1067 etr@fc322000 {
1068 compatible = "arm,coresight-tmc", "arm,primecell";
1069 reg = <0xfc322000 0x1000>;
1070
1071 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1072 clock-names = "apb_pclk", "atclk";
1073
1074 in-ports {
1075 port {
1076 etr_in: endpoint {
1077 remote-endpoint = <&replicator_out0>;
1078 };
1079 };
1080 };
1081 };
1082
1083 tpiu@fc318000 {
1084 compatible = "arm,coresight-tpiu", "arm,primecell";
1085 reg = <0xfc318000 0x1000>;
1086
1087 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1088 clock-names = "apb_pclk", "atclk";
1089
1090 in-ports {
1091 port {
1092 tpiu_in: endpoint {
1093 remote-endpoint = <&replicator_out1>;
1094 };
1095 };
1096 };
1097 };
1098
1099 replicator@fc31c000 {
1100 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1101 reg = <0xfc31c000 0x1000>;
1102
1103 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1104 clock-names = "apb_pclk", "atclk";
1105
1106 out-ports {
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109
1110 port@0 {
1111 reg = <0>;
1112 replicator_out0: endpoint {
1113 remote-endpoint = <&etr_in>;
1114 };
1115 };
1116 port@1 {
1117 reg = <1>;
1118 replicator_out1: endpoint {
1119 remote-endpoint = <&tpiu_in>;
1120 };
1121 };
1122 };
1123
1124 in-ports {
1125 port {
1126 replicator_in: endpoint {
1127 remote-endpoint = <&etf_out>;
1128 };
1129 };
1130 };
1131 };
1132
1133 etf@fc307000 {
1134 compatible = "arm,coresight-tmc", "arm,primecell";
1135 reg = <0xfc307000 0x1000>;
1136
1137 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1138 clock-names = "apb_pclk", "atclk";
1139
1140 out-ports {
1141 port {
1142 etf_out: endpoint {
1143 remote-endpoint = <&replicator_in>;
1144 };
1145 };
1146 };
1147
1148 in-ports {
1149 port {
1150 etf_in: endpoint {
1151 remote-endpoint = <&merger_out>;
1152 };
1153 };
1154 };
1155 };
1156
1157 funnel@fc31b000 {
1158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1159 reg = <0xfc31b000 0x1000>;
1160
1161 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1162 clock-names = "apb_pclk", "atclk";
1163
1164 in-ports {
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1167
1168 /*
1169 * Not described input ports:
1170 * 0 - connected trought funnel to Audio, Modem and
1171 * Resource and Power Manager CPU's
1172 * 2...7 - not-connected
1173 */
1174 port@1 {
1175 reg = <1>;
1176 merger_in1: endpoint {
1177 remote-endpoint = <&funnel1_out>;
1178 };
1179 };
1180 };
1181
1182 out-ports {
1183 port {
1184 merger_out: endpoint {
1185 remote-endpoint = <&etf_in>;
1186 };
1187 };
1188 };
1189 };
1190
1191 funnel@fc31a000 {
1192 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1193 reg = <0xfc31a000 0x1000>;
1194
1195 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1196 clock-names = "apb_pclk", "atclk";
1197
1198 in-ports {
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201
1202 /*
1203 * Not described input ports:
1204 * 0 - not-connected
1205 * 1 - connected trought funnel to Multimedia CPU
1206 * 2 - connected to Wireless CPU
1207 * 3 - not-connected
1208 * 4 - not-connected
1209 * 6 - not-connected
1210 * 7 - connected to STM
1211 */
1212 port@5 {
1213 reg = <5>;
1214 funnel1_in5: endpoint {
1215 remote-endpoint = <&kpss_out>;
1216 };
1217 };
1218 };
1219
1220 out-ports {
1221 port {
1222 funnel1_out: endpoint {
1223 remote-endpoint = <&merger_in1>;
1224 };
1225 };
1226 };
1227 };
1228
1229 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
1230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1231 reg = <0xfc345000 0x1000>;
1232
1233 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1234 clock-names = "apb_pclk", "atclk";
1235
1236 in-ports {
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1239
1240 port@0 {
1241 reg = <0>;
1242 kpss_in0: endpoint {
1243 remote-endpoint = <&etm0_out>;
1244 };
1245 };
1246 port@1 {
1247 reg = <1>;
1248 kpss_in1: endpoint {
1249 remote-endpoint = <&etm1_out>;
1250 };
1251 };
1252 port@2 {
1253 reg = <2>;
1254 kpss_in2: endpoint {
1255 remote-endpoint = <&etm2_out>;
1256 };
1257 };
1258 port@3 {
1259 reg = <3>;
1260 kpss_in3: endpoint {
1261 remote-endpoint = <&etm3_out>;
1262 };
1263 };
1264 };
1265
1266 out-ports {
1267 port {
1268 kpss_out: endpoint {
1269 remote-endpoint = <&funnel1_in5>;
1270 };
1271 };
1272 };
1273 };
1274
1275 etm@fc33c000 {
1276 compatible = "arm,coresight-etm4x", "arm,primecell";
1277 reg = <0xfc33c000 0x1000>;
1278
1279 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1280 clock-names = "apb_pclk", "atclk";
1281
1282 cpu = <&CPU0>;
1283
1284 out-ports {
1285 port {
1286 etm0_out: endpoint {
1287 remote-endpoint = <&kpss_in0>;
1288 };
1289 };
1290 };
1291 };
1292
1293 etm@fc33d000 {
1294 compatible = "arm,coresight-etm4x", "arm,primecell";
1295 reg = <0xfc33d000 0x1000>;
1296
1297 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1298 clock-names = "apb_pclk", "atclk";
1299
1300 cpu = <&CPU1>;
1301
1302 out-ports {
1303 port {
1304 etm1_out: endpoint {
1305 remote-endpoint = <&kpss_in1>;
1306 };
1307 };
1308 };
1309 };
1310
1311 etm@fc33e000 {
1312 compatible = "arm,coresight-etm4x", "arm,primecell";
1313 reg = <0xfc33e000 0x1000>;
1314
1315 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1316 clock-names = "apb_pclk", "atclk";
1317
1318 cpu = <&CPU2>;
1319
1320 out-ports {
1321 port {
1322 etm2_out: endpoint {
1323 remote-endpoint = <&kpss_in2>;
1324 };
1325 };
1326 };
1327 };
1328
1329 etm@fc33f000 {
1330 compatible = "arm,coresight-etm4x", "arm,primecell";
1331 reg = <0xfc33f000 0x1000>;
1332
1333 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1334 clock-names = "apb_pclk", "atclk";
1335
1336 cpu = <&CPU3>;
1337
1338 out-ports {
1339 port {
1340 etm3_out: endpoint {
1341 remote-endpoint = <&kpss_in3>;
1342 };
1343 };
1344 };
1345 };
1346
1347 ocmem@fdd00000 {
1348 compatible = "qcom,msm8974-ocmem";
1349 reg = <0xfdd00000 0x2000>,
1350 <0xfec00000 0x180000>;
1351 reg-names = "ctrl",
1352 "mem";
1353 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1354 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1355 clock-names = "core",
1356 "iface";
1357
1358 #address-cells = <1>;
1359 #size-cells = <1>;
1360
1361 gmu_sram: gmu-sram@0 {
1362 reg = <0x0 0x100000>;
1363 };
1364 };
1365
1366 bimc: interconnect@fc380000 {
1367 reg = <0xfc380000 0x6a000>;
1368 compatible = "qcom,msm8974-bimc";
1369 #interconnect-cells = <1>;
1370 clock-names = "bus", "bus_a";
1371 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1372 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1373 };
1374
1375 snoc: interconnect@fc460000 {
1376 reg = <0xfc460000 0x4000>;
1377 compatible = "qcom,msm8974-snoc";
1378 #interconnect-cells = <1>;
1379 clock-names = "bus", "bus_a";
1380 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1381 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1382 };
1383
1384 pnoc: interconnect@fc468000 {
1385 reg = <0xfc468000 0x4000>;
1386 compatible = "qcom,msm8974-pnoc";
1387 #interconnect-cells = <1>;
1388 clock-names = "bus", "bus_a";
1389 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1390 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1391 };
1392
1393 ocmemnoc: interconnect@fc470000 {
1394 reg = <0xfc470000 0x4000>;
1395 compatible = "qcom,msm8974-ocmemnoc";
1396 #interconnect-cells = <1>;
1397 clock-names = "bus", "bus_a";
1398 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1399 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1400 };
1401
1402 mmssnoc: interconnect@fc478000 {
1403 reg = <0xfc478000 0x4000>;
1404 compatible = "qcom,msm8974-mmssnoc";
1405 #interconnect-cells = <1>;
1406 clock-names = "bus", "bus_a";
1407 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1408 <&mmcc MMSS_S0_AXI_CLK>;
1409 };
1410
1411 cnoc: interconnect@fc480000 {
1412 reg = <0xfc480000 0x4000>;
1413 compatible = "qcom,msm8974-cnoc";
1414 #interconnect-cells = <1>;
1415 clock-names = "bus", "bus_a";
1416 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1417 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1418 };
1419
1420 gpu: adreno@fdb00000 {
1421 status = "disabled";
1422
1423 compatible = "qcom,adreno-330.1",
1424 "qcom,adreno";
1425 reg = <0xfdb00000 0x10000>;
1426 reg-names = "kgsl_3d0_reg_memory";
1427 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1428 interrupt-names = "kgsl_3d0_irq";
1429 clock-names = "core",
1430 "iface",
1431 "mem_iface";
1432 clocks = <&mmcc OXILI_GFX3D_CLK>,
1433 <&mmcc OXILICX_AHB_CLK>,
1434 <&mmcc OXILICX_AXI_CLK>;
1435 sram = <&gmu_sram>;
1436 power-domains = <&mmcc OXILICX_GDSC>;
1437 operating-points-v2 = <&gpu_opp_table>;
1438
1439 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
1440 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
1441 interconnect-names = "gfx-mem",
1442 "ocmem";
1443
1444 // iommus = <&gpu_iommu 0>;
1445
1446 gpu_opp_table: opp_table {
1447 compatible = "operating-points-v2";
1448
1449 opp-320000000 {
1450 opp-hz = /bits/ 64 <320000000>;
1451 };
1452
1453 opp-200000000 {
1454 opp-hz = /bits/ 64 <200000000>;
1455 };
1456
1457 opp-27000000 {
1458 opp-hz = /bits/ 64 <27000000>;
1459 };
1460 };
1461 };
1462
1463 mdss: mdss@fd900000 {
1464 status = "disabled";
1465
1466 compatible = "qcom,mdss";
1467 reg = <0xfd900000 0x100>,
1468 <0xfd924000 0x1000>;
1469 reg-names = "mdss_phys",
1470 "vbif_phys";
1471
1472 power-domains = <&mmcc MDSS_GDSC>;
1473
1474 clocks = <&mmcc MDSS_AHB_CLK>,
1475 <&mmcc MDSS_AXI_CLK>,
1476 <&mmcc MDSS_VSYNC_CLK>;
1477 clock-names = "iface",
1478 "bus",
1479 "vsync";
1480
1481 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1482
1483 interrupt-controller;
1484 #interrupt-cells = <1>;
1485
1486 #address-cells = <1>;
1487 #size-cells = <1>;
1488 ranges;
1489
1490 mdp: mdp@fd900000 {
1491 status = "disabled";
1492
1493 compatible = "qcom,mdp5";
1494 reg = <0xfd900100 0x22000>;
1495 reg-names = "mdp_phys";
1496
1497 interrupt-parent = <&mdss>;
1498 interrupts = <0 0>;
1499
1500 clocks = <&mmcc MDSS_AHB_CLK>,
1501 <&mmcc MDSS_AXI_CLK>,
1502 <&mmcc MDSS_MDP_CLK>,
1503 <&mmcc MDSS_VSYNC_CLK>;
1504 clock-names = "iface",
1505 "bus",
1506 "core",
1507 "vsync";
1508
1509 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1510 interconnect-names = "mdp0-mem";
1511
1512 ports {
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515
1516 port@0 {
1517 reg = <0>;
1518 mdp5_intf1_out: endpoint {
1519 remote-endpoint = <&dsi0_in>;
1520 };
1521 };
1522 };
1523 };
1524
1525 dsi0: dsi@fd922800 {
1526 status = "disabled";
1527
1528 compatible = "qcom,mdss-dsi-ctrl";
1529 reg = <0xfd922800 0x1f8>;
1530 reg-names = "dsi_ctrl";
1531
1532 interrupt-parent = <&mdss>;
1533 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1534
1535 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1536 <&mmcc PCLK0_CLK_SRC>;
1537 assigned-clock-parents = <&dsi_phy0 0>,
1538 <&dsi_phy0 1>;
1539
1540 clocks = <&mmcc MDSS_MDP_CLK>,
1541 <&mmcc MDSS_AHB_CLK>,
1542 <&mmcc MDSS_AXI_CLK>,
1543 <&mmcc MDSS_BYTE0_CLK>,
1544 <&mmcc MDSS_PCLK0_CLK>,
1545 <&mmcc MDSS_ESC0_CLK>,
1546 <&mmcc MMSS_MISC_AHB_CLK>;
1547 clock-names = "mdp_core",
1548 "iface",
1549 "bus",
1550 "byte",
1551 "pixel",
1552 "core",
1553 "core_mmss";
1554
1555 phys = <&dsi_phy0>;
1556 phy-names = "dsi-phy";
1557
1558 ports {
1559 #address-cells = <1>;
1560 #size-cells = <0>;
1561
1562 port@0 {
1563 reg = <0>;
1564 dsi0_in: endpoint {
1565 remote-endpoint = <&mdp5_intf1_out>;
1566 };
1567 };
1568
1569 port@1 {
1570 reg = <1>;
1571 dsi0_out: endpoint {
1572 };
1573 };
1574 };
1575 };
1576
1577 dsi_phy0: dsi-phy@fd922a00 {
1578 status = "disabled";
1579
1580 compatible = "qcom,dsi-phy-28nm-hpm";
1581 reg = <0xfd922a00 0xd4>,
1582 <0xfd922b00 0x280>,
1583 <0xfd922d80 0x30>;
1584 reg-names = "dsi_pll",
1585 "dsi_phy",
1586 "dsi_phy_regulator";
1587
1588 #clock-cells = <1>;
1589 #phy-cells = <0>;
1590 qcom,dsi-phy-index = <0>;
1591
1592 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1593 clock-names = "iface", "ref";
1594 };
1595 };
1596
1597 imem@fe805000 {
1598 status = "disabled";
1599 compatible = "syscon", "simple-mfd";
1600 reg = <0xfe805000 0x1000>;
1601
1602 reboot-mode {
1603 compatible = "syscon-reboot-mode";
1604 offset = <0x65c>;
1605 };
1606 };
1607 };
1608
1609 smd {
1610 compatible = "qcom,smd";
1611
1612 rpm {
1613 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1614 qcom,ipc = <&apcs 8 0>;
1615 qcom,smd-edge = <15>;
1616
1617 rpm_requests {
1618 compatible = "qcom,rpm-msm8974";
1619 qcom,smd-channels = "rpm_requests";
1620
1621 rpmcc: clock-controller {
1622 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1623 #clock-cells = <1>;
1624 };
1625
1626 pm8841-regulators {
1627 compatible = "qcom,rpm-pm8841-regulators";
1628
1629 pm8841_s1: s1 {};
1630 pm8841_s2: s2 {};
1631 pm8841_s3: s3 {};
1632 pm8841_s4: s4 {};
1633 pm8841_s5: s5 {};
1634 pm8841_s6: s6 {};
1635 pm8841_s7: s7 {};
1636 pm8841_s8: s8 {};
1637 };
1638
1639 pm8941-regulators {
1640 compatible = "qcom,rpm-pm8941-regulators";
1641
1642 pm8941_s1: s1 {};
1643 pm8941_s2: s2 {};
1644 pm8941_s3: s3 {};
1645
1646 pm8941_l1: l1 {};
1647 pm8941_l2: l2 {};
1648 pm8941_l3: l3 {};
1649 pm8941_l4: l4 {};
1650 pm8941_l5: l5 {};
1651 pm8941_l6: l6 {};
1652 pm8941_l7: l7 {};
1653 pm8941_l8: l8 {};
1654 pm8941_l9: l9 {};
1655 pm8941_l10: l10 {};
1656 pm8941_l11: l11 {};
1657 pm8941_l12: l12 {};
1658 pm8941_l13: l13 {};
1659 pm8941_l14: l14 {};
1660 pm8941_l15: l15 {};
1661 pm8941_l16: l16 {};
1662 pm8941_l17: l17 {};
1663 pm8941_l18: l18 {};
1664 pm8941_l19: l19 {};
1665 pm8941_l20: l20 {};
1666 pm8941_l21: l21 {};
1667 pm8941_l22: l22 {};
1668 pm8941_l23: l23 {};
1669 pm8941_l24: l24 {};
1670
1671 pm8941_lvs1: lvs1 {};
1672 pm8941_lvs2: lvs2 {};
1673 pm8941_lvs3: lvs3 {};
1674 };
1675 };
1676 };
1677 };
1678
1679 vreg_boost: vreg-boost {
1680 compatible = "regulator-fixed";
1681
1682 regulator-name = "vreg-boost";
1683 regulator-min-microvolt = <3150000>;
1684 regulator-max-microvolt = <3150000>;
1685
1686 regulator-always-on;
1687 regulator-boot-on;
1688
1689 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1690 enable-active-high;
1691
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&boost_bypass_n_pin>;
1694 };
1695 vreg_vph_pwr: vreg-vph-pwr {
1696 compatible = "regulator-fixed";
1697 regulator-name = "vph-pwr";
1698
1699 regulator-min-microvolt = <3600000>;
1700 regulator-max-microvolt = <3600000>;
1701
1702 regulator-always-on;
1703 };
1704};