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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author:
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7 */
8
9#ifndef _XHCI_MTK_H_
10#define _XHCI_MTK_H_
11
12#include <linux/clk.h>
13#include <linux/hashtable.h>
14
15#include "xhci.h"
16
17#define BULK_CLKS_NUM 5
18
19/* support at most 64 ep, use 32 size hash table */
20#define SCH_EP_HASH_BITS 5
21
22/**
23 * To simplify scheduler algorithm, set a upper limit for ESIT,
24 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
25 * round down to the limit value, that means allocating more
26 * bandwidth to it.
27 */
28#define XHCI_MTK_MAX_ESIT (1 << 6)
29#define XHCI_MTK_BW_INDEX(x) ((x) & (XHCI_MTK_MAX_ESIT - 1))
30
31/**
32 * @fs_bus_bw: array to keep track of bandwidth already used for FS
33 * @ep_list: Endpoints using this TT
34 */
35struct mu3h_sch_tt {
36 u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
37 struct list_head ep_list;
38};
39
40/**
41 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
42 *
43 * @bus_bw: array to keep track of bandwidth already used at each uframes
44 *
45 * treat a HS root port as a bandwidth domain, but treat a SS root port as
46 * two bandwidth domains, one for IN eps and another for OUT eps.
47 */
48struct mu3h_sch_bw_info {
49 u32 bus_bw[XHCI_MTK_MAX_ESIT];
50};
51
52/**
53 * struct mu3h_sch_ep_info: schedule information for endpoint
54 *
55 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
56 * @num_esit: number of @esit in a period
57 * @num_budget_microframes: number of continuous uframes
58 * (@repeat==1) scheduled within the interval
59 * @bw_cost_per_microframe: bandwidth cost per microframe
60 * @hentry: hash table entry
61 * @endpoint: linked into bandwidth domain which it belongs to
62 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
63 * @bw_info: bandwidth domain which this endpoint belongs
64 * @sch_tt: mu3h_sch_tt linked into
65 * @ep_type: endpoint type
66 * @maxpkt: max packet size of endpoint
67 * @ep: address of usb_host_endpoint struct
68 * @allocated: the bandwidth is aready allocated from bus_bw
69 * @offset: which uframe of the interval that transfer should be
70 * scheduled first time within the interval
71 * @repeat: the time gap between two uframes that transfers are
72 * scheduled within a interval. in the simple algorithm, only
73 * assign 0 or 1 to it; 0 means using only one uframe in a
74 * interval, and 1 means using @num_budget_microframes
75 * continuous uframes
76 * @pkts: number of packets to be transferred in the scheduled uframes
77 * @cs_count: number of CS that host will trigger
78 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
79 * distribute the bMaxBurst+1 packets for a single burst
80 * according to @pkts and @repeat, repeate the burst multiple
81 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
82 * according to @pkts and @repeat. normal mode is used by
83 * default
84 * @bw_budget_table: table to record bandwidth budget per microframe
85 */
86struct mu3h_sch_ep_info {
87 u32 esit;
88 u32 num_esit;
89 u32 num_budget_microframes;
90 u32 bw_cost_per_microframe;
91 struct list_head endpoint;
92 struct hlist_node hentry;
93 struct list_head tt_endpoint;
94 struct mu3h_sch_bw_info *bw_info;
95 struct mu3h_sch_tt *sch_tt;
96 u32 ep_type;
97 u32 maxpkt;
98 struct usb_host_endpoint *ep;
99 enum usb_device_speed speed;
100 bool allocated;
101 /*
102 * mtk xHCI scheduling information put into reserved DWs
103 * in ep context
104 */
105 u32 offset;
106 u32 repeat;
107 u32 pkts;
108 u32 cs_count;
109 u32 burst_mode;
110 u32 bw_budget_table[];
111};
112
113#define MU3C_U3_PORT_MAX 4
114#define MU3C_U2_PORT_MAX 5
115
116/**
117 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
118 * @ip_pw_ctr0~3: ip power and clock control registers
119 * @ip_pw_sts1~2: ip power and clock status registers
120 * @ip_xhci_cap: ip xHCI capability register
121 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
122 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
123 * @u2_phy_pll: usb2 phy pll control register
124 */
125struct mu3c_ippc_regs {
126 __le32 ip_pw_ctr0;
127 __le32 ip_pw_ctr1;
128 __le32 ip_pw_ctr2;
129 __le32 ip_pw_ctr3;
130 __le32 ip_pw_sts1;
131 __le32 ip_pw_sts2;
132 __le32 reserved0[3];
133 __le32 ip_xhci_cap;
134 __le32 reserved1[2];
135 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
136 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
137 __le32 reserved2;
138 __le32 u2_phy_pll;
139 __le32 reserved3[33]; /* 0x80 ~ 0xff */
140};
141
142struct xhci_hcd_mtk {
143 struct device *dev;
144 struct usb_hcd *hcd;
145 struct mu3h_sch_bw_info *sch_array;
146 struct list_head bw_ep_chk_list;
147 DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
148 struct mu3c_ippc_regs __iomem *ippc_regs;
149 int num_u2_ports;
150 int num_u3_ports;
151 int u2p_dis_msk;
152 int u3p_dis_msk;
153 struct regulator *vusb33;
154 struct regulator *vbus;
155 struct clk_bulk_data clks[BULK_CLKS_NUM];
156 unsigned int has_ippc:1;
157 unsigned int lpm_support:1;
158 unsigned int u2_lpm_disable:1;
159 /* usb remote wakeup */
160 unsigned int uwk_en:1;
161 struct regmap *uwk;
162 u32 uwk_reg_base;
163 u32 uwk_vers;
164};
165
166static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
167{
168 return dev_get_drvdata(hcd->self.controller);
169}
170
171int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
172void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
173int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
174 struct usb_host_endpoint *ep);
175int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
176 struct usb_host_endpoint *ep);
177int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
178void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
179
180#endif /* _XHCI_MTK_H_ */