tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT7622 Pin Controller Device Tree Bindings
8
9maintainers:
10 - Sean Wang <sean.wang@kernel.org>
11
12description: |+
13 The MediaTek's MT7622 Pin controller is used to control SoC pins.
14
15properties:
16 compatible:
17 enum:
18 - mediatek,mt7622-pinctrl
19 - mediatek,mt7629-pinctrl
20
21 reg:
22 maxItems: 1
23
24 reg-names:
25 items:
26 - const: eint
27
28 gpio-controller: true
29
30 "#gpio-cells":
31 const: 2
32 description: |
33 Number of cells in GPIO specifier. Since the generic GPIO
34 binding is used, the amount of cells must be specified as 2. See the below
35 mentioned gpio binding representation for description of particular cells.
36
37 interrupt-controller: true
38
39 interrupts:
40 maxItems: 1
41
42 "#interrupt-cells":
43 const: 2
44
45required:
46 - compatible
47 - reg
48 - gpio-controller
49 - "#gpio-cells"
50
51if:
52 required:
53 - interrupt-controller
54then:
55 required:
56 - reg-names
57 - interrupts
58 - "#interrupt-cells"
59
60patternProperties:
61 '-[0-9]+$':
62 type: object
63 additionalProperties: false
64 patternProperties:
65 'mux':
66 type: object
67 additionalProperties: false
68 description: |
69 pinmux configuration nodes.
70 $ref: "/schemas/pinctrl/pinmux-node.yaml"
71 properties:
72 function:
73 description: |
74 A string containing the name of the function to mux to the group.
75 enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd,
76 spi, tdm, uart, watchdog, wifi]
77
78 groups:
79 description: |
80 An array of strings. Each string contains the name of a group.
81
82 drive-strength:
83 enum: [4, 8, 12, 16]
84
85 required:
86 - groups
87 - function
88
89 allOf:
90 - if:
91 properties:
92 function:
93 const: emmc
94 then:
95 properties:
96 groups:
97 enum: [emmc, emmc_rst]
98 - if:
99 properties:
100 function:
101 const: eth
102 then:
103 properties:
104 groups:
105 enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,
106 rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]
107 - if:
108 properties:
109 function:
110 const: i2c
111 then:
112 properties:
113 groups:
114 enum: [i2c0, i2c_0, i2c_1, i2c1_0, i2c1_1, i2c1_2, i2c2_0,
115 i2c2_1, i2c2_2]
116 - if:
117 properties:
118 function:
119 const: i2s
120 then:
121 properties:
122 groups:
123 enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,
124 i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,
125 i2s1_out_data, i2s2_out_data, i2s3_out_data,
126 i2s4_out_data]
127 - if:
128 properties:
129 function:
130 const: ir
131 then:
132 properties:
133 groups:
134 enum: [ir_0_tx, ir_1_tx, ir_2_tx, ir_0_rx, ir_1_rx, ir_2_rx]
135 - if:
136 properties:
137 function:
138 const: led
139 then:
140 properties:
141 groups:
142 enum: [ephy_leds, ephy0_led, ephy1_led, ephy2_led, ephy3_led,
143 ephy4_led, wled, wf2g_led, wf5g_led]
144 - if:
145 properties:
146 function:
147 const: flash
148 then:
149 properties:
150 groups:
151 enum: [par_nand, snfi, spi_nor]
152 - if:
153 properties:
154 function:
155 const: pcie
156 then:
157 properties:
158 groups:
159 enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,
160 pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,
161 pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,
162 pcie_wake, pcie_clkreq]
163 - if:
164 properties:
165 function:
166 const: pmic
167 then:
168 properties:
169 groups:
170 enum: [pmic_bus]
171 - if:
172 properties:
173 function:
174 const: pwm
175 then:
176 properties:
177 groups:
178 enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,
179 pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,
180 pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,
181 pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,
182 pwm_ch7_0, pwm_0, pwm_1]
183 - if:
184 properties:
185 function:
186 const: sd
187 then:
188 properties:
189 groups:
190 enum: [sd_0, sd_1]
191 - if:
192 properties:
193 function:
194 const: spi
195 then:
196 properties:
197 groups:
198 enum: [spic0_0, spic0_1, spic1_0, spic1_1, spic2_0_wp_hold,
199 spic2_0, spi_0, spi_1, spi_wp, spi_hold]
200 - if:
201 properties:
202 function:
203 const: tdm
204 then:
205 properties:
206 groups:
207 enum: [tdm_0_out_mclk_bclk_ws, tdm_0_in_mclk_bclk_ws,
208 tdm_0_out_data, tdm_0_in_data, tdm_1_out_mclk_bclk_ws,
209 tdm_1_in_mclk_bclk_ws, tdm_1_out_data, tdm_1_in_data]
210 - if:
211 properties:
212 function:
213 const: uart
214 then:
215 properties:
216 groups:
217 enum: [uart0_0_tx_rx, uart1_0_tx_rx, uart1_0_rts_cts,
218 uart1_1_tx_rx, uart1_1_rts_cts, uart2_0_tx_rx,
219 uart2_0_rts_cts, uart2_1_tx_rx, uart2_1_rts_cts,
220 uart2_2_tx_rx, uart2_2_rts_cts, uart2_3_tx_rx,
221 uart3_0_tx_rx, uart3_1_tx_rx, uart3_1_rts_cts,
222 uart4_0_tx_rx, uart4_1_tx_rx, uart4_1_rts_cts,
223 uart4_2_tx_rx, uart4_2_rts_cts, uart0_txd_rxd,
224 uart1_0_txd_rxd, uart1_0_cts_rts, uart1_1_txd_rxd,
225 uart1_1_cts_rts, uart2_0_txd_rxd, uart2_0_cts_rts,
226 uart2_1_txd_rxd, uart2_1_cts_rts]
227 - if:
228 properties:
229 function:
230 const: watchdog
231 then:
232 properties:
233 groups:
234 enum: [watchdog]
235 - if:
236 properties:
237 function:
238 const: wifi
239 then:
240 properties:
241 groups:
242 enum: [wf0_2g, wf0_5g]
243
244 'conf':
245 type: object
246 additionalProperties: false
247 description: |
248 pinconf configuration nodes.
249 $ref: "/schemas/pinctrl/pincfg-node.yaml"
250
251 properties:
252 groups:
253 description: |
254 An array of strings. Each string contains the name of a group.
255 Valid values are the same as the pinmux node.
256
257 pins:
258 description: |
259 An array of strings. Each string contains the name of a pin.
260 enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,
261 RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,
262 I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,
263 I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
264 G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,
265 G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,
266 NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,
267 MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,
268 MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,
269 MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,
270 MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,
271 PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,
272 GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,
273 PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,
274 AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,
275 PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,
276 WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,
277 WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,
278 EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,
279 EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,
280 WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,
281 UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,
282 UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,
283 PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,
284 GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,
285 TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,
286 WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]
287
288 bias-disable: true
289
290 bias-pull-up: true
291
292 bias-pull-down: true
293
294 input-enable: true
295
296 input-disable: true
297
298 output-enable: true
299
300 output-low: true
301
302 output-high: true
303
304 input-schmitt-enable: true
305
306 input-schmitt-disable: true
307
308 drive-strength:
309 enum: [4, 8, 12, 16]
310
311 slew-rate:
312 enum: [0, 1]
313
314 mediatek,tdsel:
315 description: |
316 An integer describing the steps for output level shifter duty
317 cycle when asserted (high pulse width adjustment). Valid arguments
318 are from 0 to 15.
319 $ref: /schemas/types.yaml#/definitions/uint32
320
321 mediatek,rdsel:
322 description: |
323 An integer describing the steps for input level shifter duty cycle
324 when asserted (high pulse width adjustment). Valid arguments are
325 from 0 to 63.
326 $ref: /schemas/types.yaml#/definitions/uint32
327
328 required:
329 - pins
330
331additionalProperties: false
332
333examples:
334 - |
335 #include <dt-bindings/interrupt-controller/irq.h>
336 #include <dt-bindings/interrupt-controller/arm-gic.h>
337
338 soc {
339 #address-cells = <2>;
340 #size-cells = <2>;
341
342 pio: pinctrl@10211000 {
343 compatible = "mediatek,mt7622-pinctrl";
344 reg = <0 0x10211000 0 0x1000>;
345 gpio-controller;
346 #gpio-cells = <2>;
347
348 pinctrl_eth_default: eth-0 {
349 mux-mdio {
350 groups = "mdc_mdio";
351 function = "eth";
352 drive-strength = <12>;
353 };
354
355 mux-gmac2 {
356 groups = "rgmii_via_gmac2";
357 function = "eth";
358 drive-strength = <12>;
359 };
360
361 mux-esw {
362 groups = "esw";
363 function = "eth";
364 drive-strength = <8>;
365 };
366
367 conf-mdio {
368 pins = "MDC";
369 bias-pull-up;
370 };
371 };
372 };
373 };