tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner R40 TCON TOP Device Tree Bindings
8
9maintainers:
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
12
13description: |
14 TCON TOPs main purpose is to configure whole display pipeline. It
15 determines relationships between mixers and TCONs, selects source
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
18
19 It allows display pipeline to be configured in very different ways:
20
21 / LCD0/LVDS0
22 / [0] TCON-LCD0
23 | \ MIPI DSI
24 mixer0 |
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
27 / \ [2] TCON-TV0 [0] - TVE0/RGB
28 mixer1 | \
29 | TCON-TOP - HDMI
30 | /
31 \ [3] TCON-TV1 [1] - TVE1/RGB
32
33 Note that both TCON TOP references same physical unit. Both mixers
34 can be connected to any TCON. Not all TCON TOP variants support all
35 features.
36
37properties:
38 "#clock-cells":
39 const: 1
40
41 compatible:
42 enum:
43 - allwinner,sun8i-r40-tcon-top
44 - allwinner,sun50i-h6-tcon-top
45
46 reg:
47 maxItems: 1
48
49 clocks:
50 minItems: 2
51 items:
52 - description: The TCON TOP interface clock
53 - description: The TCON TOP TV0 clock
54 - description: The TCON TOP TVE0 clock
55 - description: The TCON TOP TV1 clock
56 - description: The TCON TOP TVE1 clock
57 - description: The TCON TOP MIPI DSI clock
58
59 clock-names:
60 minItems: 2
61 items:
62 - const: bus
63 - const: tcon-tv0
64 - const: tve0
65 - const: tcon-tv1
66 - const: tve1
67 - const: dsi
68
69 clock-output-names:
70 minItems: 1
71 maxItems: 3
72 description: >
73 The first item is the name of the clock created for the TV0
74 channel, the second item is the name of the TCON TV1 channel
75 clock and the third one is the name of the DSI channel clock.
76
77 resets:
78 maxItems: 1
79
80 ports:
81 $ref: /schemas/graph.yaml#/properties/ports
82
83 properties:
84 port@0:
85 $ref: /schemas/graph.yaml#/properties/port
86 description: |
87 Input endpoint for Mixer 0 mux.
88
89 port@1:
90 $ref: /schemas/graph.yaml#/properties/port
91 description: |
92 Output endpoint for Mixer 0 mux
93
94 port@2:
95 $ref: /schemas/graph.yaml#/properties/port
96 description: |
97 Input endpoint for Mixer 1 mux.
98
99 port@3:
100 $ref: /schemas/graph.yaml#/properties/port
101 description: |
102 Output endpoint for Mixer 1 mux
103
104 port@4:
105 $ref: /schemas/graph.yaml#/properties/port
106 description: |
107 Input endpoint for HDMI mux.
108
109 port@5:
110 $ref: /schemas/graph.yaml#/properties/port
111 description: |
112 Output endpoint for HDMI mux
113
114 required:
115 - port@0
116 - port@1
117 - port@4
118 - port@5
119
120required:
121 - "#clock-cells"
122 - compatible
123 - reg
124 - clocks
125 - clock-names
126 - clock-output-names
127 - resets
128 - ports
129
130additionalProperties: false
131
132if:
133 properties:
134 compatible:
135 contains:
136 const: allwinner,sun50i-h6-tcon-top
137
138then:
139 properties:
140 clocks:
141 maxItems: 2
142
143 clock-output-names:
144 maxItems: 1
145
146else:
147 properties:
148 clocks:
149 minItems: 6
150
151 clock-output-names:
152 minItems: 3
153
154 ports:
155 required:
156 - port@2
157 - port@3
158
159examples:
160 - |
161 #include <dt-bindings/interrupt-controller/arm-gic.h>
162
163 #include <dt-bindings/clock/sun8i-r40-ccu.h>
164 #include <dt-bindings/reset/sun8i-r40-ccu.h>
165
166 tcon_top: tcon-top@1c70000 {
167 compatible = "allwinner,sun8i-r40-tcon-top";
168 reg = <0x01c70000 0x1000>;
169 clocks = <&ccu CLK_BUS_TCON_TOP>,
170 <&ccu CLK_TCON_TV0>,
171 <&ccu CLK_TVE0>,
172 <&ccu CLK_TCON_TV1>,
173 <&ccu CLK_TVE1>,
174 <&ccu CLK_DSI_DPHY>;
175 clock-names = "bus",
176 "tcon-tv0",
177 "tve0",
178 "tcon-tv1",
179 "tve1",
180 "dsi";
181 clock-output-names = "tcon-top-tv0",
182 "tcon-top-tv1",
183 "tcon-top-dsi";
184 resets = <&ccu RST_BUS_TCON_TOP>;
185 #clock-cells = <1>;
186
187 ports {
188 #address-cells = <1>;
189 #size-cells = <0>;
190
191 tcon_top_mixer0_in: port@0 {
192 reg = <0>;
193
194 tcon_top_mixer0_in_mixer0: endpoint {
195 remote-endpoint = <&mixer0_out_tcon_top>;
196 };
197 };
198
199 tcon_top_mixer0_out: port@1 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <1>;
203
204 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
205 reg = <0>;
206 };
207
208 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
209 reg = <1>;
210 };
211
212 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
213 reg = <2>;
214 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
215 };
216
217 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
218 reg = <3>;
219 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
220 };
221 };
222
223 tcon_top_mixer1_in: port@2 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <2>;
227
228 tcon_top_mixer1_in_mixer1: endpoint@1 {
229 reg = <1>;
230 remote-endpoint = <&mixer1_out_tcon_top>;
231 };
232 };
233
234 tcon_top_mixer1_out: port@3 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <3>;
238
239 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
240 reg = <0>;
241 };
242
243 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
244 reg = <1>;
245 };
246
247 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
248 reg = <2>;
249 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
250 };
251
252 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
253 reg = <3>;
254 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
255 };
256 };
257
258 tcon_top_hdmi_in: port@4 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 reg = <4>;
262
263 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
264 reg = <0>;
265 remote-endpoint = <&tcon_tv0_out_tcon_top>;
266 };
267
268 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
269 reg = <1>;
270 remote-endpoint = <&tcon_tv1_out_tcon_top>;
271 };
272 };
273
274 tcon_top_hdmi_out: port@5 {
275 reg = <5>;
276
277 tcon_top_hdmi_out_hdmi: endpoint {
278 remote-endpoint = <&hdmi_in_tcon_top>;
279 };
280 };
281 };
282 };
283
284...