Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#ifndef MEMORY_TEGRA_MC_H
7#define MEMORY_TEGRA_MC_H
8
9#include <linux/bits.h>
10#include <linux/io.h>
11#include <linux/types.h>
12
13#include <soc/tegra/mc.h>
14
15#define MC_INTSTATUS 0x00
16#define MC_INTMASK 0x04
17#define MC_ERR_STATUS 0x08
18#define MC_ERR_ADR 0x0c
19#define MC_GART_ERROR_REQ 0x30
20#define MC_EMEM_ADR_CFG 0x54
21#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22#define MC_SECURITY_VIOLATION_STATUS 0x74
23#define MC_EMEM_ARB_CFG 0x90
24#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
25#define MC_EMEM_ARB_TIMING_RCD 0x98
26#define MC_EMEM_ARB_TIMING_RP 0x9c
27#define MC_EMEM_ARB_TIMING_RC 0xa0
28#define MC_EMEM_ARB_TIMING_RAS 0xa4
29#define MC_EMEM_ARB_TIMING_FAW 0xa8
30#define MC_EMEM_ARB_TIMING_RRD 0xac
31#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
32#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
33#define MC_EMEM_ARB_TIMING_R2R 0xb8
34#define MC_EMEM_ARB_TIMING_W2W 0xbc
35#define MC_EMEM_ARB_TIMING_R2W 0xc0
36#define MC_EMEM_ARB_TIMING_W2R 0xc4
37#define MC_EMEM_ARB_MISC2 0xc8
38#define MC_EMEM_ARB_DA_TURNS 0xd0
39#define MC_EMEM_ARB_DA_COVERS 0xd4
40#define MC_EMEM_ARB_MISC0 0xd8
41#define MC_EMEM_ARB_MISC1 0xdc
42#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
43#define MC_EMEM_ARB_OVERRIDE 0xe8
44#define MC_TIMING_CONTROL_DBG 0xf8
45#define MC_TIMING_CONTROL 0xfc
46
47#define MC_INT_DECERR_MTS BIT(16)
48#define MC_INT_SECERR_SEC BIT(13)
49#define MC_INT_DECERR_VPR BIT(12)
50#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11)
51#define MC_INT_INVALID_SMMU_PAGE BIT(10)
52#define MC_INT_ARBITRATION_EMEM BIT(9)
53#define MC_INT_SECURITY_VIOLATION BIT(8)
54#define MC_INT_INVALID_GART_PAGE BIT(7)
55#define MC_INT_DECERR_EMEM BIT(6)
56
57#define MC_ERR_STATUS_TYPE_SHIFT 28
58#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
59#define MC_ERR_STATUS_TYPE_MASK (0x7 << 28)
60#define MC_ERR_STATUS_READABLE BIT(27)
61#define MC_ERR_STATUS_WRITABLE BIT(26)
62#define MC_ERR_STATUS_NONSECURE BIT(25)
63#define MC_ERR_STATUS_ADR_HI_SHIFT 20
64#define MC_ERR_STATUS_ADR_HI_MASK 0x3
65#define MC_ERR_STATUS_SECURITY BIT(17)
66#define MC_ERR_STATUS_RW BIT(16)
67
68#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
69
70#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
71#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
72
73#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
74#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
75#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
76
77#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
78
79#define MC_TIMING_UPDATE BIT(0)
80
81static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents)
82{
83 val = val * percents;
84 do_div(val, 100);
85
86 return min_t(u64, val, U32_MAX);
87}
88
89static inline struct tegra_mc *
90icc_provider_to_tegra_mc(struct icc_provider *provider)
91{
92 return container_of(provider, struct tegra_mc, provider);
93}
94
95static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
96{
97 return readl_relaxed(mc->regs + offset);
98}
99
100static inline void mc_writel(const struct tegra_mc *mc, u32 value,
101 unsigned long offset)
102{
103 writel_relaxed(value, mc->regs + offset);
104}
105
106extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
107
108#ifdef CONFIG_ARCH_TEGRA_2x_SOC
109extern const struct tegra_mc_soc tegra20_mc_soc;
110#endif
111
112#ifdef CONFIG_ARCH_TEGRA_3x_SOC
113extern const struct tegra_mc_soc tegra30_mc_soc;
114#endif
115
116#ifdef CONFIG_ARCH_TEGRA_114_SOC
117extern const struct tegra_mc_soc tegra114_mc_soc;
118#endif
119
120#ifdef CONFIG_ARCH_TEGRA_124_SOC
121extern const struct tegra_mc_soc tegra124_mc_soc;
122#endif
123
124#ifdef CONFIG_ARCH_TEGRA_132_SOC
125extern const struct tegra_mc_soc tegra132_mc_soc;
126#endif
127
128#ifdef CONFIG_ARCH_TEGRA_210_SOC
129extern const struct tegra_mc_soc tegra210_mc_soc;
130#endif
131
132#ifdef CONFIG_ARCH_TEGRA_186_SOC
133extern const struct tegra_mc_soc tegra186_mc_soc;
134#endif
135
136#ifdef CONFIG_ARCH_TEGRA_194_SOC
137extern const struct tegra_mc_soc tegra194_mc_soc;
138#endif
139
140#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
141 defined(CONFIG_ARCH_TEGRA_114_SOC) || \
142 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
143 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
144 defined(CONFIG_ARCH_TEGRA_210_SOC)
145int tegra30_mc_probe(struct tegra_mc *mc);
146extern const struct tegra_mc_ops tegra30_mc_ops;
147#endif
148
149#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
150 defined(CONFIG_ARCH_TEGRA_194_SOC)
151extern const struct tegra_mc_ops tegra186_mc_ops;
152#endif
153
154extern const char * const tegra_mc_status_names[32];
155extern const char * const tegra_mc_error_names[8];
156
157/*
158 * These IDs are for internal use of Tegra ICC drivers. The ID numbers are
159 * chosen such that they don't conflict with the device-tree ICC node IDs.
160 */
161#define TEGRA_ICC_MC 1000
162#define TEGRA_ICC_EMC 1001
163#define TEGRA_ICC_EMEM 1002
164
165#endif /* MEMORY_TEGRA_MC_H */