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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: |
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
9 Controller device
10
11maintainers:
12 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13 - Lukasz Luba <lukasz.luba@arm.com>
14
15description: |
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
17 DRAM memory chips are connected. The driver is to monitor the controller in
18 runtime and switch frequency and voltage. To monitor the usage of the
19 controller in runtime, the driver uses the PPMU (Platform Performance
20 Monitoring Unit), which is able to measure the current load of the memory.
21 When 'userspace' governor is used for the driver, an application is able to
22 switch the DMC and memory frequency.
23
24properties:
25 compatible:
26 items:
27 - const: samsung,exynos5422-dmc
28
29 clock-names:
30 items:
31 - const: fout_spll
32 - const: mout_sclk_spll
33 - const: ff_dout_spll2
34 - const: fout_bpll
35 - const: mout_bpll
36 - const: sclk_bpll
37 - const: mout_mx_mspll_ccore
38 - const: mout_mclk_cdrex
39
40 clocks:
41 minItems: 8
42 maxItems: 8
43
44 devfreq-events:
45 $ref: '/schemas/types.yaml#/definitions/phandle-array'
46 minItems: 1
47 maxItems: 16
48 description: phandles of the PPMU events used by the controller.
49
50 device-handle:
51 $ref: '/schemas/types.yaml#/definitions/phandle'
52 description: |
53 phandle of the connected DRAM memory device. For more information please
54 refer to documentation file:
55 Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
56
57 operating-points-v2: true
58
59 interrupts:
60 items:
61 - description: DMC internal performance event counters in DREX0
62 - description: DMC internal performance event counters in DREX1
63
64 interrupt-names:
65 items:
66 - const: drex_0
67 - const: drex_1
68
69 reg:
70 items:
71 - description: registers of DREX0
72 - description: registers of DREX1
73
74 samsung,syscon-clk:
75 $ref: '/schemas/types.yaml#/definitions/phandle'
76 description: |
77 Phandle of the clock register set used by the controller, these registers
78 are used for enabling a 'pause' feature and are not exposed by clock
79 framework but they must be used in a safe way. The register offsets are
80 in the driver code and specyfic for this SoC type.
81
82 vdd-supply: true
83
84required:
85 - compatible
86 - clock-names
87 - clocks
88 - devfreq-events
89 - device-handle
90 - reg
91 - samsung,syscon-clk
92
93additionalProperties: false
94
95examples:
96 - |
97 #include <dt-bindings/clock/exynos5420.h>
98 ppmu_dmc0_0: ppmu@10d00000 {
99 compatible = "samsung,exynos-ppmu";
100 reg = <0x10d00000 0x2000>;
101 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
102 clock-names = "ppmu";
103 events {
104 ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
105 event-name = "ppmu-event3-dmc0_0";
106 };
107 };
108 };
109
110 memory-controller@10c20000 {
111 compatible = "samsung,exynos5422-dmc";
112 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
113 clocks = <&clock CLK_FOUT_SPLL>,
114 <&clock CLK_MOUT_SCLK_SPLL>,
115 <&clock CLK_FF_DOUT_SPLL2>,
116 <&clock CLK_FOUT_BPLL>,
117 <&clock CLK_MOUT_BPLL>,
118 <&clock CLK_SCLK_BPLL>,
119 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
120 <&clock CLK_MOUT_MCLK_CDREX>;
121 clock-names = "fout_spll",
122 "mout_sclk_spll",
123 "ff_dout_spll2",
124 "fout_bpll",
125 "mout_bpll",
126 "sclk_bpll",
127 "mout_mx_mspll_ccore",
128 "mout_mclk_cdrex";
129 operating-points-v2 = <&dmc_opp_table>;
130 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
131 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
132 device-handle = <&samsung_K3QF2F20DB>;
133 vdd-supply = <&buck1_reg>;
134 samsung,syscon-clk = <&clock>;
135 interrupt-parent = <&combiner>;
136 interrupts = <16 0>, <16 1>;
137 interrupt-names = "drex_0", "drex_1";
138 };