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1/* SPDX-License-Identifier: GPL-2.0 */
2
3#ifndef __TI_SYSC_DATA_H__
4#define __TI_SYSC_DATA_H__
5
6enum ti_sysc_module_type {
7 TI_SYSC_OMAP2,
8 TI_SYSC_OMAP2_TIMER,
9 TI_SYSC_OMAP3_SHAM,
10 TI_SYSC_OMAP3_AES,
11 TI_SYSC_OMAP4,
12 TI_SYSC_OMAP4_TIMER,
13 TI_SYSC_OMAP4_SIMPLE,
14 TI_SYSC_OMAP34XX_SR,
15 TI_SYSC_OMAP36XX_SR,
16 TI_SYSC_OMAP4_SR,
17 TI_SYSC_OMAP4_MCASP,
18 TI_SYSC_OMAP4_USB_HOST_FS,
19 TI_SYSC_DRA7_MCAN,
20 TI_SYSC_PRUSS,
21};
22
23struct ti_sysc_cookie {
24 void *data;
25 void *clkdm;
26};
27
28/**
29 * struct sysc_regbits - TI OCP_SYSCONFIG register field offsets
30 * @midle_shift: Offset of the midle bit
31 * @clkact_shift: Offset of the clockactivity bit
32 * @sidle_shift: Offset of the sidle bit
33 * @enwkup_shift: Offset of the enawakeup bit
34 * @srst_shift: Offset of the softreset bit
35 * @autoidle_shift: Offset of the autoidle bit
36 * @dmadisable_shift: Offset of the dmadisable bit
37 * @emufree_shift; Offset of the emufree bit
38 *
39 * Note that 0 is a valid shift, and for ti-sysc.c -ENODEV can be used if a
40 * feature is not available.
41 */
42struct sysc_regbits {
43 s8 midle_shift;
44 s8 clkact_shift;
45 s8 sidle_shift;
46 s8 enwkup_shift;
47 s8 srst_shift;
48 s8 autoidle_shift;
49 s8 dmadisable_shift;
50 s8 emufree_shift;
51};
52
53#define SYSC_QUIRK_REINIT_ON_RESUME BIT(27)
54#define SYSC_QUIRK_GPMC_DEBUG BIT(26)
55#define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25)
56#define SYSC_MODULE_QUIRK_PRUSS BIT(24)
57#define SYSC_MODULE_QUIRK_DSS_RESET BIT(23)
58#define SYSC_MODULE_QUIRK_RTC_UNLOCK BIT(22)
59#define SYSC_QUIRK_CLKDM_NOAUTO BIT(21)
60#define SYSC_QUIRK_FORCE_MSTANDBY BIT(20)
61#define SYSC_MODULE_QUIRK_AESS BIT(19)
62#define SYSC_MODULE_QUIRK_SGX BIT(18)
63#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
64#define SYSC_MODULE_QUIRK_I2C BIT(16)
65#define SYSC_MODULE_QUIRK_WDT BIT(15)
66#define SYSS_QUIRK_RESETDONE_INVERTED BIT(14)
67#define SYSC_QUIRK_SWSUP_MSTANDBY BIT(13)
68#define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12)
69#define SYSC_QUIRK_SWSUP_SIDLE BIT(11)
70#define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10)
71#define SYSC_QUIRK_LEGACY_IDLE BIT(9)
72#define SYSC_QUIRK_RESET_STATUS BIT(8)
73#define SYSC_QUIRK_NO_IDLE BIT(7)
74#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
75#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
76#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
77#define SYSC_QUIRK_OPT_CLKS_IN_RESET BIT(3)
78#define SYSC_QUIRK_16BIT BIT(2)
79#define SYSC_QUIRK_UNCACHED BIT(1)
80#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
81
82#define SYSC_NR_IDLEMODES 4
83
84/**
85 * struct sysc_capabilities - capabilities for an interconnect target module
86 * @type: sysc type identifier for the module
87 * @sysc_mask: bitmask of supported SYSCONFIG register bits
88 * @regbits: bitmask of SYSCONFIG register bits
89 * @mod_quirks: bitmask of module specific quirks
90 */
91struct sysc_capabilities {
92 const enum ti_sysc_module_type type;
93 const u32 sysc_mask;
94 const struct sysc_regbits *regbits;
95 const u32 mod_quirks;
96};
97
98/**
99 * struct sysc_config - configuration for an interconnect target module
100 * @sysc_val: configured value for sysc register
101 * @syss_mask: configured mask value for SYSSTATUS register
102 * @midlemodes: bitmask of supported master idle modes
103 * @sidlemodes: bitmask of supported slave idle modes
104 * @srst_udelay: optional delay needed after OCP soft reset
105 * @quirks: bitmask of enabled quirks
106 */
107struct sysc_config {
108 u32 sysc_val;
109 u32 syss_mask;
110 u8 midlemodes;
111 u8 sidlemodes;
112 u8 srst_udelay;
113 u32 quirks;
114};
115
116enum sysc_registers {
117 SYSC_REVISION,
118 SYSC_SYSCONFIG,
119 SYSC_SYSSTATUS,
120 SYSC_MAX_REGS,
121};
122
123/**
124 * struct ti_sysc_module_data - ti-sysc to hwmod translation data for a module
125 * @name: legacy "ti,hwmods" module name
126 * @module_pa: physical address of the interconnect target module
127 * @module_size: size of the interconnect target module
128 * @offsets: array of register offsets as listed in enum sysc_registers
129 * @nr_offsets: number of registers
130 * @cap: interconnect target module capabilities
131 * @cfg: interconnect target module configuration
132 *
133 * This data is enough to allocate a new struct omap_hwmod_class_sysconfig
134 * based on device tree data parsed by ti-sysc driver.
135 */
136struct ti_sysc_module_data {
137 const char *name;
138 u64 module_pa;
139 u32 module_size;
140 int *offsets;
141 int nr_offsets;
142 const struct sysc_capabilities *cap;
143 struct sysc_config *cfg;
144};
145
146struct device;
147struct clk;
148
149struct ti_sysc_platform_data {
150 struct of_dev_auxdata *auxdata;
151 bool (*soc_type_gp)(void);
152 int (*init_clockdomain)(struct device *dev, struct clk *fck,
153 struct clk *ick, struct ti_sysc_cookie *cookie);
154 void (*clkdm_deny_idle)(struct device *dev,
155 const struct ti_sysc_cookie *cookie);
156 void (*clkdm_allow_idle)(struct device *dev,
157 const struct ti_sysc_cookie *cookie);
158 int (*init_module)(struct device *dev,
159 const struct ti_sysc_module_data *data,
160 struct ti_sysc_cookie *cookie);
161 int (*enable_module)(struct device *dev,
162 const struct ti_sysc_cookie *cookie);
163 int (*idle_module)(struct device *dev,
164 const struct ti_sysc_cookie *cookie);
165 int (*shutdown_module)(struct device *dev,
166 const struct ti_sysc_cookie *cookie);
167};
168
169#endif /* __TI_SYSC_DATA_H__ */