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Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2019 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#include <linux/err.h>
17
18#define ZYNQMP_PM_VERSION_MAJOR 1
19#define ZYNQMP_PM_VERSION_MINOR 0
20
21#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24#define ZYNQMP_TZ_VERSION_MAJOR 1
25#define ZYNQMP_TZ_VERSION_MINOR 0
26
27#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30/* SMC SIP service Call Function Identifier Prefix */
31#define PM_SIP_SVC 0xC2000000
32#define PM_GET_TRUSTZONE_VERSION 0xa03
33#define PM_SET_SUSPEND_MODE 0xa02
34#define GET_CALLBACK_DATA 0xa01
35
36/* Number of 32bits values in payload */
37#define PAYLOAD_ARG_CNT 4U
38
39/* Number of arguments for a callback */
40#define CB_ARG_CNT 4
41
42/* Payload size (consists of callback API ID + arguments) */
43#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
44
45#define ZYNQMP_PM_MAX_QOS 100U
46
47#define GSS_NUM_REGS (4)
48
49/* Node capabilities */
50#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
51#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
52#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
53#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
54
55/* Loader commands */
56#define PM_LOAD_PDI 0x701
57#define PDI_SRC_DDR 0xF
58
59/*
60 * Firmware FPGA Manager flags
61 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
62 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
63 */
64#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
65#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
66
67enum pm_api_id {
68 PM_GET_API_VERSION = 1,
69 PM_SYSTEM_SHUTDOWN = 12,
70 PM_REQUEST_NODE = 13,
71 PM_RELEASE_NODE = 14,
72 PM_SET_REQUIREMENT = 15,
73 PM_RESET_ASSERT = 17,
74 PM_RESET_GET_STATUS = 18,
75 PM_PM_INIT_FINALIZE = 21,
76 PM_FPGA_LOAD = 22,
77 PM_FPGA_GET_STATUS = 23,
78 PM_GET_CHIPID = 24,
79 PM_PINCTRL_REQUEST = 28,
80 PM_PINCTRL_RELEASE = 29,
81 PM_PINCTRL_GET_FUNCTION = 30,
82 PM_PINCTRL_SET_FUNCTION = 31,
83 PM_PINCTRL_CONFIG_PARAM_GET = 32,
84 PM_PINCTRL_CONFIG_PARAM_SET = 33,
85 PM_IOCTL = 34,
86 PM_QUERY_DATA = 35,
87 PM_CLOCK_ENABLE = 36,
88 PM_CLOCK_DISABLE = 37,
89 PM_CLOCK_GETSTATE = 38,
90 PM_CLOCK_SETDIVIDER = 39,
91 PM_CLOCK_GETDIVIDER = 40,
92 PM_CLOCK_SETRATE = 41,
93 PM_CLOCK_GETRATE = 42,
94 PM_CLOCK_SETPARENT = 43,
95 PM_CLOCK_GETPARENT = 44,
96 PM_SECURE_AES = 47,
97 PM_FEATURE_CHECK = 63,
98};
99
100/* PMU-FW return status codes */
101enum pm_ret_status {
102 XST_PM_SUCCESS = 0,
103 XST_PM_NO_FEATURE = 19,
104 XST_PM_INTERNAL = 2000,
105 XST_PM_CONFLICT = 2001,
106 XST_PM_NO_ACCESS = 2002,
107 XST_PM_INVALID_NODE = 2003,
108 XST_PM_DOUBLE_REQ = 2004,
109 XST_PM_ABORT_SUSPEND = 2005,
110 XST_PM_MULT_USER = 2008,
111};
112
113enum pm_ioctl_id {
114 IOCTL_SD_DLL_RESET = 6,
115 IOCTL_SET_SD_TAPDELAY = 7,
116 IOCTL_SET_PLL_FRAC_MODE = 8,
117 IOCTL_GET_PLL_FRAC_MODE = 9,
118 IOCTL_SET_PLL_FRAC_DATA = 10,
119 IOCTL_GET_PLL_FRAC_DATA = 11,
120 IOCTL_WRITE_GGS = 12,
121 IOCTL_READ_GGS = 13,
122 IOCTL_WRITE_PGGS = 14,
123 IOCTL_READ_PGGS = 15,
124 /* Set healthy bit value */
125 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
126};
127
128enum pm_query_id {
129 PM_QID_INVALID = 0,
130 PM_QID_CLOCK_GET_NAME = 1,
131 PM_QID_CLOCK_GET_TOPOLOGY = 2,
132 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
133 PM_QID_CLOCK_GET_PARENTS = 4,
134 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
135 PM_QID_PINCTRL_GET_NUM_PINS = 6,
136 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
137 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
138 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
139 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
140 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
141 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
142 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
143};
144
145enum zynqmp_pm_reset_action {
146 PM_RESET_ACTION_RELEASE = 0,
147 PM_RESET_ACTION_ASSERT = 1,
148 PM_RESET_ACTION_PULSE = 2,
149};
150
151enum zynqmp_pm_reset {
152 ZYNQMP_PM_RESET_START = 1000,
153 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
154 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
155 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
156 ZYNQMP_PM_RESET_DP = 1003,
157 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
158 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
159 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
160 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
161 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
162 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
163 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
164 ZYNQMP_PM_RESET_GDMA = 1011,
165 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
166 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
167 ZYNQMP_PM_RESET_GPU = 1014,
168 ZYNQMP_PM_RESET_GT = 1015,
169 ZYNQMP_PM_RESET_SATA = 1016,
170 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
171 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
172 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
173 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
174 ZYNQMP_PM_RESET_APU_L2 = 1021,
175 ZYNQMP_PM_RESET_ACPU3 = 1022,
176 ZYNQMP_PM_RESET_ACPU2 = 1023,
177 ZYNQMP_PM_RESET_ACPU1 = 1024,
178 ZYNQMP_PM_RESET_ACPU0 = 1025,
179 ZYNQMP_PM_RESET_DDR = 1026,
180 ZYNQMP_PM_RESET_APM_FPD = 1027,
181 ZYNQMP_PM_RESET_SOFT = 1028,
182 ZYNQMP_PM_RESET_GEM0 = 1029,
183 ZYNQMP_PM_RESET_GEM1 = 1030,
184 ZYNQMP_PM_RESET_GEM2 = 1031,
185 ZYNQMP_PM_RESET_GEM3 = 1032,
186 ZYNQMP_PM_RESET_QSPI = 1033,
187 ZYNQMP_PM_RESET_UART0 = 1034,
188 ZYNQMP_PM_RESET_UART1 = 1035,
189 ZYNQMP_PM_RESET_SPI0 = 1036,
190 ZYNQMP_PM_RESET_SPI1 = 1037,
191 ZYNQMP_PM_RESET_SDIO0 = 1038,
192 ZYNQMP_PM_RESET_SDIO1 = 1039,
193 ZYNQMP_PM_RESET_CAN0 = 1040,
194 ZYNQMP_PM_RESET_CAN1 = 1041,
195 ZYNQMP_PM_RESET_I2C0 = 1042,
196 ZYNQMP_PM_RESET_I2C1 = 1043,
197 ZYNQMP_PM_RESET_TTC0 = 1044,
198 ZYNQMP_PM_RESET_TTC1 = 1045,
199 ZYNQMP_PM_RESET_TTC2 = 1046,
200 ZYNQMP_PM_RESET_TTC3 = 1047,
201 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
202 ZYNQMP_PM_RESET_NAND = 1049,
203 ZYNQMP_PM_RESET_ADMA = 1050,
204 ZYNQMP_PM_RESET_GPIO = 1051,
205 ZYNQMP_PM_RESET_IOU_CC = 1052,
206 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
207 ZYNQMP_PM_RESET_RPU_R50 = 1054,
208 ZYNQMP_PM_RESET_RPU_R51 = 1055,
209 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
210 ZYNQMP_PM_RESET_OCM = 1057,
211 ZYNQMP_PM_RESET_RPU_PGE = 1058,
212 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
213 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
214 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
215 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
216 ZYNQMP_PM_RESET_USB0_APB = 1063,
217 ZYNQMP_PM_RESET_USB1_APB = 1064,
218 ZYNQMP_PM_RESET_IPI = 1065,
219 ZYNQMP_PM_RESET_APM_LPD = 1066,
220 ZYNQMP_PM_RESET_RTC = 1067,
221 ZYNQMP_PM_RESET_SYSMON = 1068,
222 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
223 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
224 ZYNQMP_PM_RESET_FPD = 1071,
225 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
226 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
227 ZYNQMP_PM_RESET_DBG_LPD = 1074,
228 ZYNQMP_PM_RESET_DBG_FPD = 1075,
229 ZYNQMP_PM_RESET_APLL = 1076,
230 ZYNQMP_PM_RESET_DPLL = 1077,
231 ZYNQMP_PM_RESET_VPLL = 1078,
232 ZYNQMP_PM_RESET_IOPLL = 1079,
233 ZYNQMP_PM_RESET_RPLL = 1080,
234 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
235 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
236 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
237 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
238 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
239 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
240 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
241 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
242 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
243 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
244 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
245 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
246 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
247 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
248 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
249 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
250 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
251 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
252 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
253 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
254 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
255 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
256 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
257 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
258 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
259 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
260 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
261 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
262 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
263 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
264 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
265 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
266 ZYNQMP_PM_RESET_RPU_LS = 1113,
267 ZYNQMP_PM_RESET_PS_ONLY = 1114,
268 ZYNQMP_PM_RESET_PL = 1115,
269 ZYNQMP_PM_RESET_PS_PL0 = 1116,
270 ZYNQMP_PM_RESET_PS_PL1 = 1117,
271 ZYNQMP_PM_RESET_PS_PL2 = 1118,
272 ZYNQMP_PM_RESET_PS_PL3 = 1119,
273 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
274};
275
276enum zynqmp_pm_suspend_reason {
277 SUSPEND_POWER_REQUEST = 201,
278 SUSPEND_ALERT = 202,
279 SUSPEND_SYSTEM_SHUTDOWN = 203,
280};
281
282enum zynqmp_pm_request_ack {
283 ZYNQMP_PM_REQUEST_ACK_NO = 1,
284 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
285 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
286};
287
288enum pm_node_id {
289 NODE_SD_0 = 39,
290 NODE_SD_1 = 40,
291};
292
293enum tap_delay_type {
294 PM_TAPDELAY_INPUT = 0,
295 PM_TAPDELAY_OUTPUT = 1,
296};
297
298enum dll_reset_type {
299 PM_DLL_RESET_ASSERT = 0,
300 PM_DLL_RESET_RELEASE = 1,
301 PM_DLL_RESET_PULSE = 2,
302};
303
304enum pm_pinctrl_config_param {
305 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
306 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
307 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
308 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
309 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
310 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
311 PM_PINCTRL_CONFIG_TRI_STATE = 6,
312 PM_PINCTRL_CONFIG_MAX = 7,
313};
314
315enum pm_pinctrl_slew_rate {
316 PM_PINCTRL_SLEW_RATE_FAST = 0,
317 PM_PINCTRL_SLEW_RATE_SLOW = 1,
318};
319
320enum pm_pinctrl_bias_status {
321 PM_PINCTRL_BIAS_DISABLE = 0,
322 PM_PINCTRL_BIAS_ENABLE = 1,
323};
324
325enum pm_pinctrl_pull_ctrl {
326 PM_PINCTRL_BIAS_PULL_DOWN = 0,
327 PM_PINCTRL_BIAS_PULL_UP = 1,
328};
329
330enum pm_pinctrl_schmitt_cmos {
331 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
332 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
333};
334
335enum pm_pinctrl_drive_strength {
336 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
337 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
338 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
339 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
340};
341
342enum zynqmp_pm_shutdown_type {
343 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
344 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
345 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
346};
347
348enum zynqmp_pm_shutdown_subtype {
349 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
350 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
351 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
352};
353
354/**
355 * struct zynqmp_pm_query_data - PM query data
356 * @qid: query ID
357 * @arg1: Argument 1 of query data
358 * @arg2: Argument 2 of query data
359 * @arg3: Argument 3 of query data
360 */
361struct zynqmp_pm_query_data {
362 u32 qid;
363 u32 arg1;
364 u32 arg2;
365 u32 arg3;
366};
367
368int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
369 u32 arg2, u32 arg3, u32 *ret_payload);
370
371#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
372int zynqmp_pm_get_api_version(u32 *version);
373int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
374int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
375int zynqmp_pm_clock_enable(u32 clock_id);
376int zynqmp_pm_clock_disable(u32 clock_id);
377int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
378int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
379int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
380int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
381int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
382int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
383int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
384int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
385int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
386int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
387int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
388int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
389int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
390int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
391 const enum zynqmp_pm_reset_action assert_flag);
392int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
393int zynqmp_pm_init_finalize(void);
394int zynqmp_pm_set_suspend_mode(u32 mode);
395int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
396 const u32 qos, const enum zynqmp_pm_request_ack ack);
397int zynqmp_pm_release_node(const u32 node);
398int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
399 const u32 qos,
400 const enum zynqmp_pm_request_ack ack);
401int zynqmp_pm_aes_engine(const u64 address, u32 *out);
402int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
403int zynqmp_pm_fpga_get_status(u32 *value);
404int zynqmp_pm_write_ggs(u32 index, u32 value);
405int zynqmp_pm_read_ggs(u32 index, u32 *value);
406int zynqmp_pm_write_pggs(u32 index, u32 value);
407int zynqmp_pm_read_pggs(u32 index, u32 *value);
408int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
409int zynqmp_pm_set_boot_health_status(u32 value);
410int zynqmp_pm_pinctrl_request(const u32 pin);
411int zynqmp_pm_pinctrl_release(const u32 pin);
412int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
413int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
414int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
415 u32 *value);
416int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
417 u32 value);
418int zynqmp_pm_load_pdi(const u32 src, const u64 address);
419#else
420static inline int zynqmp_pm_get_api_version(u32 *version)
421{
422 return -ENODEV;
423}
424
425static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
426{
427 return -ENODEV;
428}
429
430static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
431 u32 *out)
432{
433 return -ENODEV;
434}
435
436static inline int zynqmp_pm_clock_enable(u32 clock_id)
437{
438 return -ENODEV;
439}
440
441static inline int zynqmp_pm_clock_disable(u32 clock_id)
442{
443 return -ENODEV;
444}
445
446static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
447{
448 return -ENODEV;
449}
450
451static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
452{
453 return -ENODEV;
454}
455
456static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
457{
458 return -ENODEV;
459}
460
461static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
462{
463 return -ENODEV;
464}
465
466static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
467{
468 return -ENODEV;
469}
470
471static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
472{
473 return -ENODEV;
474}
475
476static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
477{
478 return -ENODEV;
479}
480
481static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
482{
483 return -ENODEV;
484}
485
486static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
487{
488 return -ENODEV;
489}
490
491static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
492{
493 return -ENODEV;
494}
495
496static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
497{
498 return -ENODEV;
499}
500
501static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
502{
503 return -ENODEV;
504}
505
506static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
507{
508 return -ENODEV;
509}
510
511static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
512 const enum zynqmp_pm_reset_action assert_flag)
513{
514 return -ENODEV;
515}
516
517static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
518 u32 *status)
519{
520 return -ENODEV;
521}
522
523static inline int zynqmp_pm_init_finalize(void)
524{
525 return -ENODEV;
526}
527
528static inline int zynqmp_pm_set_suspend_mode(u32 mode)
529{
530 return -ENODEV;
531}
532
533static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
534 const u32 qos,
535 const enum zynqmp_pm_request_ack ack)
536{
537 return -ENODEV;
538}
539
540static inline int zynqmp_pm_release_node(const u32 node)
541{
542 return -ENODEV;
543}
544
545static inline int zynqmp_pm_set_requirement(const u32 node,
546 const u32 capabilities,
547 const u32 qos,
548 const enum zynqmp_pm_request_ack ack)
549{
550 return -ENODEV;
551}
552
553static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
554{
555 return -ENODEV;
556}
557
558static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
559 const u32 flags)
560{
561 return -ENODEV;
562}
563
564static inline int zynqmp_pm_fpga_get_status(u32 *value)
565{
566 return -ENODEV;
567}
568
569static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
570{
571 return -ENODEV;
572}
573
574static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
575{
576 return -ENODEV;
577}
578
579static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
580{
581 return -ENODEV;
582}
583
584static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
585{
586 return -ENODEV;
587}
588
589static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
590{
591 return -ENODEV;
592}
593
594static inline int zynqmp_pm_set_boot_health_status(u32 value)
595{
596 return -ENODEV;
597}
598
599static inline int zynqmp_pm_pinctrl_request(const u32 pin)
600{
601 return -ENODEV;
602}
603
604static inline int zynqmp_pm_pinctrl_release(const u32 pin)
605{
606 return -ENODEV;
607}
608
609static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
610{
611 return -ENODEV;
612}
613
614static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
615{
616 return -ENODEV;
617}
618
619static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
620 u32 *value)
621{
622 return -ENODEV;
623}
624
625static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
626 u32 value)
627{
628 return -ENODEV;
629}
630
631static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
632{
633 return -ENODEV;
634}
635#endif
636
637#endif /* __FIRMWARE_ZYNQMP_H__ */