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1Mediatek DSI Device
2===================
3
4The Mediatek DSI function block is a sink of the display subsystem and can
5drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
6channel output.
7
8Required properties:
9- compatible: "mediatek,<chip>-dsi"
10- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
11- reg: Physical base address and length of the controller's registers
12- interrupts: The interrupt signal from the function block.
13- clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15- clock-names: must contain "engine", "digital", and "hs"
16- phys: phandle link to the MIPI D-PHY controller.
17- phy-names: must contain "dphy"
18- port: Output port node with endpoint definitions as described in
19 Documentation/devicetree/bindings/graph.txt. This port should be connected
20 to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
21
22MIPI TX Configuration Module
23============================
24
25See phy/mediatek,dsi-phy.yaml
26
27Example:
28
29mipi_tx0: mipi-dphy@10215000 {
30 compatible = "mediatek,mt8173-mipi-tx";
31 reg = <0 0x10215000 0 0x1000>;
32 clocks = <&clk26m>;
33 clock-output-names = "mipi_tx0_pll";
34 #clock-cells = <0>;
35 #phy-cells = <0>;
36 drive-strength-microamp = <4600>;
37 nvmem-cells= <&mipi_tx_calibration>;
38 nvmem-cell-names = "calibration-data";
39};
40
41dsi0: dsi@1401b000 {
42 compatible = "mediatek,mt8173-dsi";
43 reg = <0 0x1401b000 0 0x1000>;
44 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
45 clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
46 <&mipi_tx0>;
47 clock-names = "engine", "digital", "hs";
48 phys = <&mipi_tx0>;
49 phy-names = "dphy";
50
51 port {
52 dsi0_out: endpoint {
53 remote-endpoint = <&panel_in>;
54 };
55 };
56};