tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Last Level Cache Controller
8
9maintainers:
10 - Rishabh Bhatnagar <rishabhb@codeaurora.org>
11 - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
12
13description: |
14 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
15 that can be shared by multiple clients. Clients here are different cores in the
16 SoC, the idea is to minimize the local caches at the clients and migrate to
17 common pool of memory. Cache memory is divided into partitions called slices
18 which are assigned to clients. Clients can query the slice details, activate
19 and deactivate them.
20
21properties:
22 compatible:
23 enum:
24 - qcom,sc7180-llcc
25 - qcom,sc7280-llcc
26 - qcom,sdm845-llcc
27 - qcom,sm8150-llcc
28 - qcom,sm8250-llcc
29
30 reg:
31 items:
32 - description: LLCC base register region
33 - description: LLCC broadcast base register region
34
35 reg-names:
36 items:
37 - const: llcc_base
38 - const: llcc_broadcast_base
39
40 interrupts:
41 maxItems: 1
42
43required:
44 - compatible
45 - reg
46 - reg-names
47 - interrupts
48
49additionalProperties: false
50
51examples:
52 - |
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54
55 system-cache-controller@1100000 {
56 compatible = "qcom,sdm845-llcc";
57 reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
58 reg-names = "llcc_base", "llcc_broadcast_base";
59 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
60 };