tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 */
7
8#ifndef __QCA8K_H
9#define __QCA8K_H
10
11#include <linux/delay.h>
12#include <linux/regmap.h>
13#include <linux/gpio.h>
14
15#define QCA8K_NUM_PORTS 7
16#define QCA8K_MAX_MTU 9000
17
18#define PHY_ID_QCA8327 0x004dd034
19#define QCA8K_ID_QCA8327 0x12
20#define PHY_ID_QCA8337 0x004dd036
21#define QCA8K_ID_QCA8337 0x13
22
23#define QCA8K_BUSY_WAIT_TIMEOUT 2000
24
25#define QCA8K_NUM_FDB_RECORDS 2048
26
27#define QCA8K_CPU_PORT 0
28
29#define QCA8K_PORT_VID_DEF 1
30
31/* Global control registers */
32#define QCA8K_REG_MASK_CTRL 0x000
33#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
34#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
35#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
36#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
37#define QCA8K_REG_PORT0_PAD_CTRL 0x004
38#define QCA8K_REG_PORT5_PAD_CTRL 0x008
39#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
40#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
41#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
42#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
43#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
44#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
45#define QCA8K_MAX_DELAY 3
46#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
47#define QCA8K_REG_PWS 0x010
48#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
49#define QCA8K_REG_MODULE_EN 0x030
50#define QCA8K_MODULE_EN_MIB BIT(0)
51#define QCA8K_REG_MIB 0x034
52#define QCA8K_MIB_FLUSH BIT(24)
53#define QCA8K_MIB_CPU_KEEP BIT(20)
54#define QCA8K_MIB_BUSY BIT(17)
55#define QCA8K_MDIO_MASTER_CTRL 0x3c
56#define QCA8K_MDIO_MASTER_BUSY BIT(31)
57#define QCA8K_MDIO_MASTER_EN BIT(30)
58#define QCA8K_MDIO_MASTER_READ BIT(27)
59#define QCA8K_MDIO_MASTER_WRITE 0
60#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
61#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
62#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
63#define QCA8K_MDIO_MASTER_DATA(x) (x)
64#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
65#define QCA8K_MDIO_MASTER_MAX_PORTS 5
66#define QCA8K_MDIO_MASTER_MAX_REG 32
67#define QCA8K_GOL_MAC_ADDR0 0x60
68#define QCA8K_GOL_MAC_ADDR1 0x64
69#define QCA8K_MAX_FRAME_SIZE 0x78
70#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
71#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
72#define QCA8K_PORT_STATUS_SPEED_10 0
73#define QCA8K_PORT_STATUS_SPEED_100 0x1
74#define QCA8K_PORT_STATUS_SPEED_1000 0x2
75#define QCA8K_PORT_STATUS_TXMAC BIT(2)
76#define QCA8K_PORT_STATUS_RXMAC BIT(3)
77#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
78#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
79#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
80#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
81#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
82#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
83#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
84#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
85#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
86#define QCA8K_PORT_HDR_CTRL_RX_S 2
87#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
88#define QCA8K_PORT_HDR_CTRL_TX_S 0
89#define QCA8K_PORT_HDR_CTRL_ALL 2
90#define QCA8K_PORT_HDR_CTRL_MGMT 1
91#define QCA8K_PORT_HDR_CTRL_NONE 0
92#define QCA8K_REG_SGMII_CTRL 0x0e0
93#define QCA8K_SGMII_EN_PLL BIT(1)
94#define QCA8K_SGMII_EN_RX BIT(2)
95#define QCA8K_SGMII_EN_TX BIT(3)
96#define QCA8K_SGMII_EN_SD BIT(4)
97#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
98#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
99#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
100#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
101#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
102
103/* EEE control registers */
104#define QCA8K_REG_EEE_CTRL 0x100
105#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
106
107/* ACL registers */
108#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
109#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
110#define QCA8K_PORT_VLAN_SVID(x) x
111#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
112#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
113#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
114
115/* Lookup registers */
116#define QCA8K_REG_ATU_DATA0 0x600
117#define QCA8K_ATU_ADDR2_S 24
118#define QCA8K_ATU_ADDR3_S 16
119#define QCA8K_ATU_ADDR4_S 8
120#define QCA8K_REG_ATU_DATA1 0x604
121#define QCA8K_ATU_PORT_M 0x7f
122#define QCA8K_ATU_PORT_S 16
123#define QCA8K_ATU_ADDR0_S 8
124#define QCA8K_REG_ATU_DATA2 0x608
125#define QCA8K_ATU_VID_M 0xfff
126#define QCA8K_ATU_VID_S 8
127#define QCA8K_ATU_STATUS_M 0xf
128#define QCA8K_ATU_STATUS_STATIC 0xf
129#define QCA8K_REG_ATU_FUNC 0x60c
130#define QCA8K_ATU_FUNC_BUSY BIT(31)
131#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
132#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
133#define QCA8K_ATU_FUNC_FULL BIT(12)
134#define QCA8K_ATU_FUNC_PORT_M 0xf
135#define QCA8K_ATU_FUNC_PORT_S 8
136#define QCA8K_REG_VTU_FUNC0 0x610
137#define QCA8K_VTU_FUNC0_VALID BIT(20)
138#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
139#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
140#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
141#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
142#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
143#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
144#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
145#define QCA8K_REG_VTU_FUNC1 0x614
146#define QCA8K_VTU_FUNC1_BUSY BIT(31)
147#define QCA8K_VTU_FUNC1_VID_S 16
148#define QCA8K_VTU_FUNC1_FULL BIT(4)
149#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
150#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
151#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
152#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
153#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
154#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
155#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
156#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
157#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
158#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
159#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
160#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
161#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
162#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
163#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
164#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
165#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
166#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
167#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
168#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
169#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
170#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
171
172#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
173#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
174#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
175#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
176#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
177
178#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
179#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
180#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
181#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
182#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
183#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
184#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
185#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
186#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
187#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
188#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
189#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
190#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
191#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
192#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
193
194#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
195#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
196#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
197#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
198#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
199#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
200#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
201
202/* Pkt edit registers */
203#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
204
205/* L3 registers */
206#define QCA8K_HROUTER_CONTROL 0xe00
207#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
208#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
209#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
210#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
211#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
212#define QCA8K_HNAT_CONTROL 0xe38
213
214/* MIB registers */
215#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
216
217/* QCA specific MII registers */
218#define MII_ATH_MMD_ADDR 0x0d
219#define MII_ATH_MMD_DATA 0x0e
220
221enum {
222 QCA8K_PORT_SPEED_10M = 0,
223 QCA8K_PORT_SPEED_100M = 1,
224 QCA8K_PORT_SPEED_1000M = 2,
225 QCA8K_PORT_SPEED_ERR = 3,
226};
227
228enum qca8k_fdb_cmd {
229 QCA8K_FDB_FLUSH = 1,
230 QCA8K_FDB_LOAD = 2,
231 QCA8K_FDB_PURGE = 3,
232 QCA8K_FDB_NEXT = 6,
233 QCA8K_FDB_SEARCH = 7,
234};
235
236enum qca8k_vlan_cmd {
237 QCA8K_VLAN_FLUSH = 1,
238 QCA8K_VLAN_LOAD = 2,
239 QCA8K_VLAN_PURGE = 3,
240 QCA8K_VLAN_REMOVE_PORT = 4,
241 QCA8K_VLAN_NEXT = 5,
242 QCA8K_VLAN_READ = 6,
243};
244
245struct ar8xxx_port_status {
246 int enabled;
247};
248
249struct qca8k_match_data {
250 u8 id;
251};
252
253struct qca8k_priv {
254 u8 switch_id;
255 u8 switch_revision;
256 u8 rgmii_tx_delay;
257 u8 rgmii_rx_delay;
258 bool legacy_phy_port_mapping;
259 struct regmap *regmap;
260 struct mii_bus *bus;
261 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
262 struct dsa_switch *ds;
263 struct mutex reg_mutex;
264 struct device *dev;
265 struct dsa_switch_ops ops;
266 struct gpio_desc *reset_gpio;
267 unsigned int port_mtu[QCA8K_NUM_PORTS];
268};
269
270struct qca8k_mib_desc {
271 unsigned int size;
272 unsigned int offset;
273 const char *name;
274};
275
276struct qca8k_fdb {
277 u16 vid;
278 u8 port_mask;
279 u8 aging;
280 u8 mac[6];
281};
282
283#endif /* __QCA8K_H */