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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <linux/soundwire/sdw.h>
15#include <linux/soundwire/sdw_intel.h>
16#include <sound/compress_driver.h>
17#include <sound/hda_codec.h>
18#include <sound/hdaudio_ext.h>
19#include "shim.h"
20
21/* PCI registers */
22#define PCI_TCSEL 0x44
23#define PCI_PGCTL PCI_TCSEL
24#define PCI_CGCTL 0x48
25
26/* PCI_PGCTL bits */
27#define PCI_PGCTL_ADSPPGD BIT(2)
28#define PCI_PGCTL_LSRMD_MASK BIT(4)
29
30/* PCI_CGCTL bits */
31#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
32#define PCI_CGCTL_ADSPDCGE BIT(1)
33
34/* Legacy HDA registers and bits used - widths are variable */
35#define SOF_HDA_GCAP 0x0
36#define SOF_HDA_GCTL 0x8
37/* accept unsol. response enable */
38#define SOF_HDA_GCTL_UNSOL BIT(8)
39#define SOF_HDA_LLCH 0x14
40#define SOF_HDA_INTCTL 0x20
41#define SOF_HDA_INTSTS 0x24
42#define SOF_HDA_WAKESTS 0x0E
43#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
44#define SOF_HDA_RIRBSTS 0x5d
45
46/* SOF_HDA_GCTL register bist */
47#define SOF_HDA_GCTL_RESET BIT(0)
48
49/* SOF_HDA_INCTL regs */
50#define SOF_HDA_INT_GLOBAL_EN BIT(31)
51#define SOF_HDA_INT_CTRL_EN BIT(30)
52#define SOF_HDA_INT_ALL_STREAM 0xff
53
54/* SOF_HDA_INTSTS regs */
55#define SOF_HDA_INTSTS_GIS BIT(31)
56
57#define SOF_HDA_MAX_CAPS 10
58#define SOF_HDA_CAP_ID_OFF 16
59#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
60 SOF_HDA_CAP_ID_OFF)
61#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
62
63#define SOF_HDA_GTS_CAP_ID 0x1
64#define SOF_HDA_ML_CAP_ID 0x2
65
66#define SOF_HDA_PP_CAP_ID 0x3
67#define SOF_HDA_REG_PP_PPCH 0x10
68#define SOF_HDA_REG_PP_PPCTL 0x04
69#define SOF_HDA_REG_PP_PPSTS 0x08
70#define SOF_HDA_PPCTL_PIE BIT(31)
71#define SOF_HDA_PPCTL_GPROCEN BIT(30)
72
73/*Vendor Specific Registers*/
74#define SOF_HDA_VS_D0I3C 0x104A
75
76/* D0I3C Register fields */
77#define SOF_HDA_VS_D0I3C_CIP BIT(0) /* Command-In-Progress */
78#define SOF_HDA_VS_D0I3C_I3 BIT(2) /* D0i3 enable bit */
79
80/* DPIB entry size: 8 Bytes = 2 DWords */
81#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
82
83#define SOF_HDA_SPIB_CAP_ID 0x4
84#define SOF_HDA_DRSM_CAP_ID 0x5
85
86#define SOF_HDA_SPIB_BASE 0x08
87#define SOF_HDA_SPIB_INTERVAL 0x08
88#define SOF_HDA_SPIB_SPIB 0x00
89#define SOF_HDA_SPIB_MAXFIFO 0x04
90
91#define SOF_HDA_PPHC_BASE 0x10
92#define SOF_HDA_PPHC_INTERVAL 0x10
93
94#define SOF_HDA_PPLC_BASE 0x10
95#define SOF_HDA_PPLC_MULTI 0x10
96#define SOF_HDA_PPLC_INTERVAL 0x10
97
98#define SOF_HDA_DRSM_BASE 0x08
99#define SOF_HDA_DRSM_INTERVAL 0x08
100
101/* Descriptor error interrupt */
102#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
103
104/* FIFO error interrupt */
105#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
106
107/* Buffer completion interrupt */
108#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
109
110#define SOF_HDA_CL_DMA_SD_INT_MASK \
111 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
112 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
113 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
114#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
115
116/* Intel HD Audio Code Loader DMA Registers */
117#define SOF_HDA_ADSP_LOADER_BASE 0x80
118#define SOF_HDA_ADSP_DPLBASE 0x70
119#define SOF_HDA_ADSP_DPUBASE 0x74
120#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
121
122/* Stream Registers */
123#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
124#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
125#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
126#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
127#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
128#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
129#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
130#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
131#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
132#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
133#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
134#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
135
136/* CL: Software Position Based FIFO Capability Registers */
137#define SOF_DSP_REG_CL_SPBFIFO \
138 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
139#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
140#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
141#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
142#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
143
144/* Stream Number */
145#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
146#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
147 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
148 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
149
150#define HDA_DSP_HDA_BAR 0
151#define HDA_DSP_PP_BAR 1
152#define HDA_DSP_SPIB_BAR 2
153#define HDA_DSP_DRSM_BAR 3
154#define HDA_DSP_BAR 4
155
156#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
157
158#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
159
160#define HDA_DSP_PANIC_OFFSET(x) \
161 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
162
163/* SRAM window 0 FW "registers" */
164#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
165#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
166/* FW and ROM share offset 4 */
167#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
168#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
169#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
170
171#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
172
173#define HDA_DSP_STREAM_RESET_TIMEOUT 300
174/*
175 * Timeout in us, for setting the stream RUN bit, during
176 * start/stop the stream. The timeout expires if new RUN bit
177 * value cannot be read back within the specified time.
178 */
179#define HDA_DSP_STREAM_RUN_TIMEOUT 300
180
181#define HDA_DSP_SPIB_ENABLE 1
182#define HDA_DSP_SPIB_DISABLE 0
183
184#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
185
186#define HDA_DSP_STACK_DUMP_SIZE 32
187
188/* ROM status/error values */
189#define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
190#define HDA_DSP_ROM_INIT 0x1
191#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
192#define HDA_DSP_ROM_FW_FW_LOADED 0x4
193#define HDA_DSP_ROM_FW_ENTERED 0x5
194#define HDA_DSP_ROM_RFW_START 0xf
195#define HDA_DSP_ROM_CSE_ERROR 40
196#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
197#define HDA_DSP_ROM_IMR_TO_SMALL 42
198#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
199#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
200#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
201#define HDA_DSP_ROM_L2_CACHE_ERROR 46
202#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
203#define HDA_DSP_ROM_API_PTR_INVALID 50
204#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
205#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
206#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
207#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
208#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
209#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
210#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
211#define HDA_DSP_IPC_PURGE_FW 0x01004000
212
213/* various timeout values */
214#define HDA_DSP_PU_TIMEOUT 50
215#define HDA_DSP_PD_TIMEOUT 50
216#define HDA_DSP_RESET_TIMEOUT_US 50000
217#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
218#define HDA_DSP_INIT_TIMEOUT_US 500000
219#define HDA_DSP_CTRL_RESET_TIMEOUT 100
220#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
221#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
222#define HDA_DSP_REG_POLL_RETRY_COUNT 50
223
224#define HDA_DSP_ADSPIC_IPC 1
225#define HDA_DSP_ADSPIS_IPC 1
226
227/* Intel HD Audio General DSP Registers */
228#define HDA_DSP_GEN_BASE 0x0
229#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
230#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
231#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
232#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
233#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
234
235#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
236#define HDA_DSP_REG_SNDW_WAKE_STS 0x2C192
237
238/* Intel HD Audio Inter-Processor Communication Registers */
239#define HDA_DSP_IPC_BASE 0x40
240#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
241#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
242#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
243#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
244#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
245
246/* Intel Vendor Specific Registers */
247#define HDA_VS_INTEL_EM2 0x1030
248#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
249#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
250
251/* HIPCI */
252#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
253#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
254
255/* HIPCIE */
256#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
257#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
258
259/* HIPCCTL */
260#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
261#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
262
263/* HIPCT */
264#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
265#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
266
267/* HIPCTE */
268#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
269
270#define HDA_DSP_ADSPIC_CL_DMA 0x2
271#define HDA_DSP_ADSPIS_CL_DMA 0x2
272
273/* Delay before scheduling D0i3 entry */
274#define BXT_D0I3_DELAY 5000
275
276#define FW_CL_STREAM_NUMBER 0x1
277#define HDA_FW_BOOT_ATTEMPTS 3
278
279/* ADSPCS - Audio DSP Control & Status */
280
281/*
282 * Core Reset - asserted high
283 * CRST Mask for a given core mask pattern, cm
284 */
285#define HDA_DSP_ADSPCS_CRST_SHIFT 0
286#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
287
288/*
289 * Core run/stall - when set to '1' core is stalled
290 * CSTALL Mask for a given core mask pattern, cm
291 */
292#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
293#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
294
295/*
296 * Set Power Active - when set to '1' turn cores on
297 * SPA Mask for a given core mask pattern, cm
298 */
299#define HDA_DSP_ADSPCS_SPA_SHIFT 16
300#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
301
302/*
303 * Current Power Active - power status of cores, set by hardware
304 * CPA Mask for a given core mask pattern, cm
305 */
306#define HDA_DSP_ADSPCS_CPA_SHIFT 24
307#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
308
309/*
310 * Mask for a given number of cores
311 * nc = number of supported cores
312 */
313#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
314
315/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
316#define CNL_DSP_IPC_BASE 0xc0
317#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
318#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
319#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
320#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
321#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
322#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
323#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
324
325/* HIPCI */
326#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
327#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
328
329/* HIPCIE */
330#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
331#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
332
333/* HIPCCTL */
334#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
335#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
336
337/* HIPCT */
338#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
339#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
340
341/* HIPCTDA */
342#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
343#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
344
345/* HIPCTDD */
346#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
347
348/* BDL */
349#define HDA_DSP_BDL_SIZE 4096
350#define HDA_DSP_MAX_BDL_ENTRIES \
351 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
352
353/* Number of DAIs */
354#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
355
356#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
357#define SOF_SKL_NUM_DAIS 16
358#else
359#define SOF_SKL_NUM_DAIS 15
360#endif
361
362#else
363#define SOF_SKL_NUM_DAIS 8
364#endif
365
366/* Intel HD Audio SRAM Window 0*/
367#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
368
369/* Firmware status window */
370#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
371#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
372
373/* Host Device Memory Space */
374#define APL_SSP_BASE_OFFSET 0x2000
375#define CNL_SSP_BASE_OFFSET 0x10000
376
377/* Host Device Memory Size of a Single SSP */
378#define SSP_DEV_MEM_SIZE 0x1000
379
380/* SSP Count of the Platform */
381#define APL_SSP_COUNT 6
382#define CNL_SSP_COUNT 3
383#define ICL_SSP_COUNT 6
384
385/* SSP Registers */
386#define SSP_SSC1_OFFSET 0x4
387#define SSP_SET_SCLK_SLAVE BIT(25)
388#define SSP_SET_SFRM_SLAVE BIT(24)
389#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
390
391#define HDA_IDISP_ADDR 2
392#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
393
394struct sof_intel_dsp_bdl {
395 __le32 addr_l;
396 __le32 addr_h;
397 __le32 size;
398 __le32 ioc;
399} __attribute((packed));
400
401#define SOF_HDA_PLAYBACK_STREAMS 16
402#define SOF_HDA_CAPTURE_STREAMS 16
403#define SOF_HDA_PLAYBACK 0
404#define SOF_HDA_CAPTURE 1
405
406/* stream flags */
407#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
408
409/*
410 * Time in ms for opportunistic D0I3 entry delay.
411 * This has been deliberately chosen to be long to avoid race conditions.
412 * Could be optimized in future.
413 */
414#define SOF_HDA_D0I3_WORK_DELAY_MS 5000
415
416/* HDA DSP D0 substate */
417enum sof_hda_D0_substate {
418 SOF_HDA_DSP_PM_D0I0, /* default D0 substate */
419 SOF_HDA_DSP_PM_D0I3, /* low power D0 substate */
420};
421
422/* represents DSP HDA controller frontend - i.e. host facing control */
423struct sof_intel_hda_dev {
424 int boot_iteration;
425
426 struct hda_bus hbus;
427
428 /* hw config */
429 const struct sof_intel_dsp_desc *desc;
430
431 /* trace */
432 struct hdac_ext_stream *dtrace_stream;
433
434 /* if position update IPC needed */
435 u32 no_ipc_position;
436
437 /* the maximum number of streams (playback + capture) supported */
438 u32 stream_max;
439
440 /* PM related */
441 bool l1_support_changed;/* during suspend, is L1SEN changed or not */
442
443 /* DMIC device */
444 struct platform_device *dmic_dev;
445
446 /* delayed work to enter D0I3 opportunistically */
447 struct delayed_work d0i3_work;
448
449 /* ACPI information stored between scan and probe steps */
450 struct sdw_intel_acpi_info info;
451
452 /* sdw context allocated by SoundWire driver */
453 struct sdw_intel_ctx *sdw;
454
455 /* FW clock config, 0:HPRO, 1:LPRO */
456 bool clk_config_lpro;
457};
458
459static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
460{
461 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
462
463 return &hda->hbus.core;
464}
465
466static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
467{
468 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
469
470 return &hda->hbus;
471}
472
473struct sof_intel_hda_stream {
474 struct snd_sof_dev *sdev;
475 struct hdac_ext_stream hda_stream;
476 struct sof_intel_stream stream;
477 int host_reserved; /* reserve host DMA channel */
478 u32 flags;
479};
480
481#define hstream_to_sof_hda_stream(hstream) \
482 container_of(hstream, struct sof_intel_hda_stream, hda_stream)
483
484#define bus_to_sof_hda(bus) \
485 container_of(bus, struct sof_intel_hda_dev, hbus.core)
486
487#define SOF_STREAM_SD_OFFSET(s) \
488 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
489 + SOF_HDA_ADSP_LOADER_BASE)
490
491/*
492 * DSP Core services.
493 */
494int hda_dsp_probe(struct snd_sof_dev *sdev);
495int hda_dsp_remove(struct snd_sof_dev *sdev);
496int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
497 unsigned int core_mask);
498int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
499 unsigned int core_mask);
500int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
501int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
502int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
503int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
504int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
505bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
506 unsigned int core_mask);
507int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
508 unsigned int core_mask);
509void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
510void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
511
512int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
513 const struct sof_dsp_power_state *target_state);
514
515int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
516int hda_dsp_resume(struct snd_sof_dev *sdev);
517int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
518int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
519int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
520int hda_dsp_shutdown(struct snd_sof_dev *sdev);
521int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
522void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
523void hda_ipc_dump(struct snd_sof_dev *sdev);
524void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
525void hda_dsp_d0i3_work(struct work_struct *work);
526
527/*
528 * DSP PCM Operations.
529 */
530u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
531u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
532int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
533 struct snd_pcm_substream *substream);
534int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
535 struct snd_pcm_substream *substream);
536int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
537 struct snd_pcm_substream *substream,
538 struct snd_pcm_hw_params *params,
539 struct sof_ipc_stream_params *ipc_params);
540int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
541 struct snd_pcm_substream *substream);
542int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
543 struct snd_pcm_substream *substream, int cmd);
544snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
545 struct snd_pcm_substream *substream);
546
547/*
548 * DSP Stream Operations.
549 */
550
551int hda_dsp_stream_init(struct snd_sof_dev *sdev);
552void hda_dsp_stream_free(struct snd_sof_dev *sdev);
553int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
554 struct hdac_ext_stream *stream,
555 struct snd_dma_buffer *dmab,
556 struct snd_pcm_hw_params *params);
557int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
558 struct snd_dma_buffer *dmab,
559 struct snd_pcm_hw_params *params);
560int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
561 struct hdac_ext_stream *stream, int cmd);
562irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
563int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
564 struct snd_dma_buffer *dmab,
565 struct hdac_stream *stream);
566bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
567bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
568
569struct hdac_ext_stream *
570 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
571int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
572int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
573 struct hdac_ext_stream *stream,
574 int enable, u32 size);
575
576void hda_ipc_msg_data(struct snd_sof_dev *sdev,
577 struct snd_pcm_substream *substream,
578 void *p, size_t sz);
579int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
580 struct snd_pcm_substream *substream,
581 const struct sof_ipc_pcm_params_reply *reply);
582
583#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
584/*
585 * Probe Compress Operations.
586 */
587int hda_probe_compr_assign(struct snd_sof_dev *sdev,
588 struct snd_compr_stream *cstream,
589 struct snd_soc_dai *dai);
590int hda_probe_compr_free(struct snd_sof_dev *sdev,
591 struct snd_compr_stream *cstream,
592 struct snd_soc_dai *dai);
593int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
594 struct snd_compr_stream *cstream,
595 struct snd_compr_params *params,
596 struct snd_soc_dai *dai);
597int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
598 struct snd_compr_stream *cstream, int cmd,
599 struct snd_soc_dai *dai);
600int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
601 struct snd_compr_stream *cstream,
602 struct snd_compr_tstamp *tstamp,
603 struct snd_soc_dai *dai);
604#endif
605
606/*
607 * DSP IPC Operations.
608 */
609int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
610 struct snd_sof_ipc_msg *msg);
611void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
612int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
613int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
614
615irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
616int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
617
618/*
619 * DSP Code loader.
620 */
621int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
622int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
623int hda_dsp_cl_boot_firmware_iccmax_icl(struct snd_sof_dev *sdev);
624int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
625
626/* pre and post fw run ops */
627int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
628int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
629int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev);
630int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask);
631
632/* parse platform specific ext manifest ops */
633int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
634 const struct sof_ext_man_elem_header *hdr);
635
636/*
637 * HDA Controller Operations.
638 */
639int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
640void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
641void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
642int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
643void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
644int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
645int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
646void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
647/*
648 * HDA bus operations.
649 */
650void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
651
652#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
653/*
654 * HDA Codec operations.
655 */
656void hda_codec_probe_bus(struct snd_sof_dev *sdev,
657 bool hda_codec_use_common_hdmi);
658void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
659void hda_codec_jack_check(struct snd_sof_dev *sdev);
660
661#endif /* CONFIG_SND_SOC_SOF_HDA */
662
663#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
664 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
665 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
666
667void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
668int hda_codec_i915_init(struct snd_sof_dev *sdev);
669int hda_codec_i915_exit(struct snd_sof_dev *sdev);
670
671#else
672
673static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
674 bool enable) { }
675static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
676static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
677
678#endif
679
680/*
681 * Trace Control.
682 */
683int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
684int hda_dsp_trace_release(struct snd_sof_dev *sdev);
685int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
686
687/*
688 * SoundWire support
689 */
690#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
691
692int hda_sdw_startup(struct snd_sof_dev *sdev);
693void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
694void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
695
696#else
697
698static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
699{
700 return 0;
701}
702
703static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
704{
705 return 0;
706}
707
708static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
709{
710 return 0;
711}
712
713static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
714{
715 return 0;
716}
717
718static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
719{
720}
721
722static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
723{
724 return false;
725}
726
727static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
728{
729 return IRQ_HANDLED;
730}
731
732static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
733{
734 return false;
735}
736
737static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
738{
739}
740#endif
741
742/* common dai driver */
743extern struct snd_soc_dai_driver skl_dai[];
744
745/*
746 * Platform Specific HW abstraction Ops.
747 */
748extern const struct snd_sof_dsp_ops sof_apl_ops;
749extern const struct snd_sof_dsp_ops sof_cnl_ops;
750extern const struct snd_sof_dsp_ops sof_tgl_ops;
751extern const struct snd_sof_dsp_ops sof_icl_ops;
752
753extern const struct sof_intel_dsp_desc apl_chip_info;
754extern const struct sof_intel_dsp_desc cnl_chip_info;
755extern const struct sof_intel_dsp_desc skl_chip_info;
756extern const struct sof_intel_dsp_desc icl_chip_info;
757extern const struct sof_intel_dsp_desc tgl_chip_info;
758extern const struct sof_intel_dsp_desc tglh_chip_info;
759extern const struct sof_intel_dsp_desc ehl_chip_info;
760extern const struct sof_intel_dsp_desc jsl_chip_info;
761extern const struct sof_intel_dsp_desc adls_chip_info;
762
763/* machine driver select */
764void hda_machine_select(struct snd_sof_dev *sdev);
765void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
766 struct snd_sof_dev *sdev);
767
768/* PCI driver selection and probe */
769int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
770
771#endif