tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020 BayLibre, SAS
4 * Author: Phong LE <ple@baylibre.com>
5 * Copyright (C) 2018-2019, Artem Mygaiev
6 * Copyright (C) 2017, Fresco Logic, Incorporated.
7 *
8 */
9
10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14#include <linux/bitfield.h>
15#include <linux/property.h>
16#include <linux/regmap.h>
17#include <linux/of_graph.h>
18#include <linux/gpio/consumer.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/regulator/consumer.h>
21
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_bridge.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_edid.h>
26#include <drm/drm_modes.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29
30#define IT66121_VENDOR_ID0_REG 0x00
31#define IT66121_VENDOR_ID1_REG 0x01
32#define IT66121_DEVICE_ID0_REG 0x02
33#define IT66121_DEVICE_ID1_REG 0x03
34
35#define IT66121_VENDOR_ID0 0x54
36#define IT66121_VENDOR_ID1 0x49
37#define IT66121_DEVICE_ID0 0x12
38#define IT66121_DEVICE_ID1 0x06
39#define IT66121_REVISION_MASK GENMASK(7, 4)
40#define IT66121_DEVICE_ID1_MASK GENMASK(3, 0)
41
42#define IT66121_MASTER_SEL_REG 0x10
43#define IT66121_MASTER_SEL_HOST BIT(0)
44
45#define IT66121_AFE_DRV_REG 0x61
46#define IT66121_AFE_DRV_RST BIT(4)
47#define IT66121_AFE_DRV_PWD BIT(5)
48
49#define IT66121_INPUT_MODE_REG 0x70
50#define IT66121_INPUT_MODE_RGB (0 << 6)
51#define IT66121_INPUT_MODE_YUV422 BIT(6)
52#define IT66121_INPUT_MODE_YUV444 (2 << 6)
53#define IT66121_INPUT_MODE_CCIR656 BIT(4)
54#define IT66121_INPUT_MODE_SYNCEMB BIT(3)
55#define IT66121_INPUT_MODE_DDR BIT(2)
56
57#define IT66121_INPUT_CSC_REG 0x72
58#define IT66121_INPUT_CSC_ENDITHER BIT(7)
59#define IT66121_INPUT_CSC_ENUDFILTER BIT(6)
60#define IT66121_INPUT_CSC_DNFREE_GO BIT(5)
61#define IT66121_INPUT_CSC_RGB_TO_YUV 0x02
62#define IT66121_INPUT_CSC_YUV_TO_RGB 0x03
63#define IT66121_INPUT_CSC_NO_CONV 0x00
64
65#define IT66121_AFE_XP_REG 0x62
66#define IT66121_AFE_XP_GAINBIT BIT(7)
67#define IT66121_AFE_XP_PWDPLL BIT(6)
68#define IT66121_AFE_XP_ENI BIT(5)
69#define IT66121_AFE_XP_ENO BIT(4)
70#define IT66121_AFE_XP_RESETB BIT(3)
71#define IT66121_AFE_XP_PWDI BIT(2)
72
73#define IT66121_AFE_IP_REG 0x64
74#define IT66121_AFE_IP_GAINBIT BIT(7)
75#define IT66121_AFE_IP_PWDPLL BIT(6)
76#define IT66121_AFE_IP_CKSEL_05 (0 << 4)
77#define IT66121_AFE_IP_CKSEL_1 BIT(4)
78#define IT66121_AFE_IP_CKSEL_2 (2 << 4)
79#define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4)
80#define IT66121_AFE_IP_ER0 BIT(3)
81#define IT66121_AFE_IP_RESETB BIT(2)
82#define IT66121_AFE_IP_ENC BIT(1)
83#define IT66121_AFE_IP_EC1 BIT(0)
84
85#define IT66121_AFE_XP_EC1_REG 0x68
86#define IT66121_AFE_XP_EC1_LOWCLK BIT(4)
87
88#define IT66121_SW_RST_REG 0x04
89#define IT66121_SW_RST_REF BIT(5)
90#define IT66121_SW_RST_AREF BIT(4)
91#define IT66121_SW_RST_VID BIT(3)
92#define IT66121_SW_RST_AUD BIT(2)
93#define IT66121_SW_RST_HDCP BIT(0)
94
95#define IT66121_DDC_COMMAND_REG 0x15
96#define IT66121_DDC_COMMAND_BURST_READ 0x0
97#define IT66121_DDC_COMMAND_EDID_READ 0x3
98#define IT66121_DDC_COMMAND_FIFO_CLR 0x9
99#define IT66121_DDC_COMMAND_SCL_PULSE 0xA
100#define IT66121_DDC_COMMAND_ABORT 0xF
101
102#define IT66121_HDCP_REG 0x20
103#define IT66121_HDCP_CPDESIRED BIT(0)
104#define IT66121_HDCP_EN1P1FEAT BIT(1)
105
106#define IT66121_INT_STATUS1_REG 0x06
107#define IT66121_INT_STATUS1_AUD_OVF BIT(7)
108#define IT66121_INT_STATUS1_DDC_NOACK BIT(5)
109#define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4)
110#define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2)
111#define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1)
112#define IT66121_INT_STATUS1_HPD_STATUS BIT(0)
113
114#define IT66121_DDC_HEADER_REG 0x11
115#define IT66121_DDC_HEADER_HDCP 0x74
116#define IT66121_DDC_HEADER_EDID 0xA0
117
118#define IT66121_DDC_OFFSET_REG 0x12
119#define IT66121_DDC_BYTE_REG 0x13
120#define IT66121_DDC_SEGMENT_REG 0x14
121#define IT66121_DDC_RD_FIFO_REG 0x17
122
123#define IT66121_CLK_BANK_REG 0x0F
124#define IT66121_CLK_BANK_PWROFF_RCLK BIT(6)
125#define IT66121_CLK_BANK_PWROFF_ACLK BIT(5)
126#define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4)
127#define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3)
128#define IT66121_CLK_BANK_0 0
129#define IT66121_CLK_BANK_1 1
130
131#define IT66121_INT_REG 0x05
132#define IT66121_INT_ACTIVE_HIGH BIT(7)
133#define IT66121_INT_OPEN_DRAIN BIT(6)
134#define IT66121_INT_TX_CLK_OFF BIT(0)
135
136#define IT66121_INT_MASK1_REG 0x09
137#define IT66121_INT_MASK1_AUD_OVF BIT(7)
138#define IT66121_INT_MASK1_DDC_NOACK BIT(5)
139#define IT66121_INT_MASK1_DDC_FIFOERR BIT(4)
140#define IT66121_INT_MASK1_DDC_BUSHANG BIT(2)
141#define IT66121_INT_MASK1_RX_SENS BIT(1)
142#define IT66121_INT_MASK1_HPD BIT(0)
143
144#define IT66121_INT_CLR1_REG 0x0C
145#define IT66121_INT_CLR1_PKTACP BIT(7)
146#define IT66121_INT_CLR1_PKTNULL BIT(6)
147#define IT66121_INT_CLR1_PKTGEN BIT(5)
148#define IT66121_INT_CLR1_KSVLISTCHK BIT(4)
149#define IT66121_INT_CLR1_AUTHDONE BIT(3)
150#define IT66121_INT_CLR1_AUTHFAIL BIT(2)
151#define IT66121_INT_CLR1_RX_SENS BIT(1)
152#define IT66121_INT_CLR1_HPD BIT(0)
153
154#define IT66121_AV_MUTE_REG 0xC1
155#define IT66121_AV_MUTE_ON BIT(0)
156#define IT66121_AV_MUTE_BLUESCR BIT(1)
157
158#define IT66121_PKT_GEN_CTRL_REG 0xC6
159#define IT66121_PKT_GEN_CTRL_ON BIT(0)
160#define IT66121_PKT_GEN_CTRL_RPT BIT(1)
161
162#define IT66121_AVIINFO_DB1_REG 0x158
163#define IT66121_AVIINFO_DB2_REG 0x159
164#define IT66121_AVIINFO_DB3_REG 0x15A
165#define IT66121_AVIINFO_DB4_REG 0x15B
166#define IT66121_AVIINFO_DB5_REG 0x15C
167#define IT66121_AVIINFO_CSUM_REG 0x15D
168#define IT66121_AVIINFO_DB6_REG 0x15E
169#define IT66121_AVIINFO_DB7_REG 0x15F
170#define IT66121_AVIINFO_DB8_REG 0x160
171#define IT66121_AVIINFO_DB9_REG 0x161
172#define IT66121_AVIINFO_DB10_REG 0x162
173#define IT66121_AVIINFO_DB11_REG 0x163
174#define IT66121_AVIINFO_DB12_REG 0x164
175#define IT66121_AVIINFO_DB13_REG 0x165
176
177#define IT66121_AVI_INFO_PKT_REG 0xCD
178#define IT66121_AVI_INFO_PKT_ON BIT(0)
179#define IT66121_AVI_INFO_PKT_RPT BIT(1)
180
181#define IT66121_HDMI_MODE_REG 0xC0
182#define IT66121_HDMI_MODE_HDMI BIT(0)
183
184#define IT66121_SYS_STATUS_REG 0x0E
185#define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7)
186#define IT66121_SYS_STATUS_HPDETECT BIT(6)
187#define IT66121_SYS_STATUS_SENDECTECT BIT(5)
188#define IT66121_SYS_STATUS_VID_STABLE BIT(4)
189#define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1)
190#define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0)
191
192#define IT66121_DDC_STATUS_REG 0x16
193#define IT66121_DDC_STATUS_TX_DONE BIT(7)
194#define IT66121_DDC_STATUS_ACTIVE BIT(6)
195#define IT66121_DDC_STATUS_NOACK BIT(5)
196#define IT66121_DDC_STATUS_WAIT_BUS BIT(4)
197#define IT66121_DDC_STATUS_ARBI_LOSE BIT(3)
198#define IT66121_DDC_STATUS_FIFO_FULL BIT(2)
199#define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1)
200#define IT66121_DDC_STATUS_FIFO_VALID BIT(0)
201
202#define IT66121_EDID_SLEEP_US 20000
203#define IT66121_EDID_TIMEOUT_US 200000
204#define IT66121_EDID_FIFO_SIZE 32
205#define IT66121_AFE_CLK_HIGH 80000 /* Khz */
206
207struct it66121_ctx {
208 struct regmap *regmap;
209 struct drm_bridge bridge;
210 struct drm_bridge *next_bridge;
211 struct drm_connector *connector;
212 struct device *dev;
213 struct gpio_desc *gpio_reset;
214 struct i2c_client *client;
215 struct regulator_bulk_data supplies[3];
216 u32 bus_width;
217 struct mutex lock; /* Protects fields below and device registers */
218 struct hdmi_avi_infoframe hdmi_avi_infoframe;
219};
220
221static const struct regmap_range_cfg it66121_regmap_banks[] = {
222 {
223 .name = "it66121",
224 .range_min = 0x00,
225 .range_max = 0x1FF,
226 .selector_reg = IT66121_CLK_BANK_REG,
227 .selector_mask = 0x1,
228 .selector_shift = 0,
229 .window_start = 0x00,
230 .window_len = 0x130,
231 },
232};
233
234static const struct regmap_config it66121_regmap_config = {
235 .val_bits = 8,
236 .reg_bits = 8,
237 .max_register = 0x1FF,
238 .ranges = it66121_regmap_banks,
239 .num_ranges = ARRAY_SIZE(it66121_regmap_banks),
240};
241
242static void it66121_hw_reset(struct it66121_ctx *ctx)
243{
244 gpiod_set_value(ctx->gpio_reset, 1);
245 msleep(20);
246 gpiod_set_value(ctx->gpio_reset, 0);
247}
248
249static inline int ite66121_power_on(struct it66121_ctx *ctx)
250{
251 return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
252}
253
254static inline int ite66121_power_off(struct it66121_ctx *ctx)
255{
256 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
257}
258
259static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
260{
261 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
262}
263
264static inline int it66121_fire_afe(struct it66121_ctx *ctx)
265{
266 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
267}
268
269/* TOFIX: Handle YCbCr Input & Output */
270static int it66121_configure_input(struct it66121_ctx *ctx)
271{
272 int ret;
273 u8 mode = IT66121_INPUT_MODE_RGB;
274
275 if (ctx->bus_width == 12)
276 mode |= IT66121_INPUT_MODE_DDR;
277
278 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
279 if (ret)
280 return ret;
281
282 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
283}
284
285/**
286 * it66121_configure_afe() - Configure the analog front end
287 * @ctx: it66121_ctx object
288 * @mode: mode to configure
289 *
290 * RETURNS:
291 * zero if success, a negative error code otherwise.
292 */
293static int it66121_configure_afe(struct it66121_ctx *ctx,
294 const struct drm_display_mode *mode)
295{
296 int ret;
297
298 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
299 IT66121_AFE_DRV_RST);
300 if (ret)
301 return ret;
302
303 if (mode->clock > IT66121_AFE_CLK_HIGH) {
304 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
305 IT66121_AFE_XP_GAINBIT |
306 IT66121_AFE_XP_ENO,
307 IT66121_AFE_XP_GAINBIT);
308 if (ret)
309 return ret;
310
311 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
312 IT66121_AFE_IP_GAINBIT |
313 IT66121_AFE_IP_ER0 |
314 IT66121_AFE_IP_EC1,
315 IT66121_AFE_IP_GAINBIT);
316 if (ret)
317 return ret;
318
319 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
320 IT66121_AFE_XP_EC1_LOWCLK, 0x80);
321 if (ret)
322 return ret;
323 } else {
324 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
325 IT66121_AFE_XP_GAINBIT |
326 IT66121_AFE_XP_ENO,
327 IT66121_AFE_XP_ENO);
328 if (ret)
329 return ret;
330
331 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
332 IT66121_AFE_IP_GAINBIT |
333 IT66121_AFE_IP_ER0 |
334 IT66121_AFE_IP_EC1, IT66121_AFE_IP_ER0 |
335 IT66121_AFE_IP_EC1);
336 if (ret)
337 return ret;
338
339 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
340 IT66121_AFE_XP_EC1_LOWCLK,
341 IT66121_AFE_XP_EC1_LOWCLK);
342 if (ret)
343 return ret;
344 }
345
346 /* Clear reset flags */
347 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
348 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
349 if (ret)
350 return ret;
351
352 return it66121_fire_afe(ctx);
353}
354
355static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
356{
357 int ret, val;
358 u32 busy = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
359 IT66121_DDC_STATUS_ARBI_LOSE;
360
361 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, true,
362 IT66121_EDID_SLEEP_US, IT66121_EDID_TIMEOUT_US);
363 if (ret)
364 return ret;
365
366 if (val & busy)
367 return -EAGAIN;
368
369 return 0;
370}
371
372static int it66121_clear_ddc_fifo(struct it66121_ctx *ctx)
373{
374 int ret;
375
376 ret = it66121_preamble_ddc(ctx);
377 if (ret)
378 return ret;
379
380 return regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
381 IT66121_DDC_COMMAND_FIFO_CLR);
382}
383
384static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
385{
386 int ret;
387 unsigned int swreset, cpdesire;
388
389 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
390 if (ret)
391 return ret;
392
393 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
394 if (ret)
395 return ret;
396
397 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
398 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
399 if (ret)
400 return ret;
401
402 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
403 (swreset | IT66121_SW_RST_HDCP));
404 if (ret)
405 return ret;
406
407 ret = it66121_preamble_ddc(ctx);
408 if (ret)
409 return ret;
410
411 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
412 IT66121_DDC_COMMAND_ABORT);
413 if (ret)
414 return ret;
415
416 return it66121_wait_ddc_ready(ctx);
417}
418
419static int it66121_get_edid_block(void *context, u8 *buf,
420 unsigned int block, size_t len)
421{
422 struct it66121_ctx *ctx = context;
423 unsigned int val;
424 int remain = len;
425 int offset = 0;
426 int ret, cnt;
427
428 offset = (block % 2) * len;
429 block = block / 2;
430
431 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
432 if (ret)
433 return ret;
434
435 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
436 ret = it66121_abort_ddc_ops(ctx);
437 if (ret)
438 return ret;
439 }
440
441 ret = it66121_clear_ddc_fifo(ctx);
442 if (ret)
443 return ret;
444
445 while (remain > 0) {
446 cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
447 IT66121_EDID_FIFO_SIZE : remain;
448 ret = it66121_preamble_ddc(ctx);
449 if (ret)
450 return ret;
451
452 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
453 IT66121_DDC_COMMAND_FIFO_CLR);
454 if (ret)
455 return ret;
456
457 ret = it66121_wait_ddc_ready(ctx);
458 if (ret)
459 return ret;
460
461 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
462 if (ret)
463 return ret;
464
465 if (val & IT66121_INT_STATUS1_DDC_BUSHANG) {
466 ret = it66121_abort_ddc_ops(ctx);
467 if (ret)
468 return ret;
469 }
470
471 ret = it66121_preamble_ddc(ctx);
472 if (ret)
473 return ret;
474
475 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
476 IT66121_DDC_HEADER_EDID);
477 if (ret)
478 return ret;
479
480 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
481 if (ret)
482 return ret;
483
484 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
485 if (ret)
486 return ret;
487
488 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
489 if (ret)
490 return ret;
491
492 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
493 IT66121_DDC_COMMAND_EDID_READ);
494 if (ret)
495 return ret;
496
497 offset += cnt;
498 remain -= cnt;
499
500 /* Per programming manual, sleep here before emptying the FIFO */
501 msleep(20);
502
503 ret = it66121_wait_ddc_ready(ctx);
504 if (ret)
505 return ret;
506
507 do {
508 ret = regmap_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, &val);
509 if (ret)
510 return ret;
511 *(buf++) = val;
512 cnt--;
513 } while (cnt > 0);
514 }
515
516 return 0;
517}
518
519static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
520{
521 int val;
522
523 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
524 return false;
525
526 return val & IT66121_SYS_STATUS_HPDETECT;
527}
528
529static int it66121_bridge_attach(struct drm_bridge *bridge,
530 enum drm_bridge_attach_flags flags)
531{
532 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
533 int ret;
534
535 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
536 return -EINVAL;
537
538 ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
539
540 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
541 IT66121_CLK_BANK_PWROFF_RCLK, 0);
542 if (ret)
543 return ret;
544
545 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
546 IT66121_INT_TX_CLK_OFF, 0);
547 if (ret)
548 return ret;
549
550 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
551 IT66121_AFE_DRV_PWD, 0);
552 if (ret)
553 return ret;
554
555 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
556 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
557 if (ret)
558 return ret;
559
560 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
561 IT66121_AFE_IP_PWDPLL, 0);
562 if (ret)
563 return ret;
564
565 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
566 IT66121_AFE_DRV_RST, 0);
567 if (ret)
568 return ret;
569
570 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
571 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
572 if (ret)
573 return ret;
574
575 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
576 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
577 if (ret)
578 return ret;
579
580 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
581 IT66121_SW_RST_REF,
582 IT66121_SW_RST_REF);
583 if (ret)
584 return ret;
585
586 /* Per programming manual, sleep here for bridge to settle */
587 msleep(50);
588
589 /* Start interrupts */
590 return regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
591 IT66121_INT_MASK1_DDC_NOACK |
592 IT66121_INT_MASK1_DDC_FIFOERR |
593 IT66121_INT_MASK1_DDC_BUSHANG, 0);
594}
595
596static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
597{
598 int ret;
599 unsigned int val = 0;
600
601 if (mute)
602 val = IT66121_AV_MUTE_ON;
603
604 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
605 if (ret)
606 return ret;
607
608 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
609 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
610}
611
612#define MAX_OUTPUT_SEL_FORMATS 1
613
614static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
615 struct drm_bridge_state *bridge_state,
616 struct drm_crtc_state *crtc_state,
617 struct drm_connector_state *conn_state,
618 unsigned int *num_output_fmts)
619{
620 u32 *output_fmts;
621
622 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
623 GFP_KERNEL);
624 if (!output_fmts)
625 return NULL;
626
627 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */
628 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
629 *num_output_fmts = 1;
630
631 return output_fmts;
632}
633
634#define MAX_INPUT_SEL_FORMATS 1
635
636static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
637 struct drm_bridge_state *bridge_state,
638 struct drm_crtc_state *crtc_state,
639 struct drm_connector_state *conn_state,
640 u32 output_fmt,
641 unsigned int *num_input_fmts)
642{
643 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
644 u32 *input_fmts;
645
646 *num_input_fmts = 0;
647
648 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
649 GFP_KERNEL);
650 if (!input_fmts)
651 return NULL;
652
653 if (ctx->bus_width == 12)
654 /* IT66121FN Datasheet specifies Little-Endian ordering */
655 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
656 else
657 /* TOFIX support more input bus formats in 24bit width */
658 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
659 *num_input_fmts = 1;
660
661 return input_fmts;
662}
663
664static void it66121_bridge_enable(struct drm_bridge *bridge,
665 struct drm_bridge_state *bridge_state)
666{
667 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
668 struct drm_atomic_state *state = bridge_state->base.state;
669
670 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
671
672 it66121_set_mute(ctx, false);
673}
674
675static void it66121_bridge_disable(struct drm_bridge *bridge,
676 struct drm_bridge_state *bridge_state)
677{
678 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
679
680 it66121_set_mute(ctx, true);
681
682 ctx->connector = NULL;
683}
684
685static
686void it66121_bridge_mode_set(struct drm_bridge *bridge,
687 const struct drm_display_mode *mode,
688 const struct drm_display_mode *adjusted_mode)
689{
690 int ret, i;
691 u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
692 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
693 const u16 aviinfo_reg[HDMI_AVI_INFOFRAME_SIZE] = {
694 IT66121_AVIINFO_DB1_REG,
695 IT66121_AVIINFO_DB2_REG,
696 IT66121_AVIINFO_DB3_REG,
697 IT66121_AVIINFO_DB4_REG,
698 IT66121_AVIINFO_DB5_REG,
699 IT66121_AVIINFO_DB6_REG,
700 IT66121_AVIINFO_DB7_REG,
701 IT66121_AVIINFO_DB8_REG,
702 IT66121_AVIINFO_DB9_REG,
703 IT66121_AVIINFO_DB10_REG,
704 IT66121_AVIINFO_DB11_REG,
705 IT66121_AVIINFO_DB12_REG,
706 IT66121_AVIINFO_DB13_REG
707 };
708
709 mutex_lock(&ctx->lock);
710
711 hdmi_avi_infoframe_init(&ctx->hdmi_avi_infoframe);
712
713 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
714 adjusted_mode);
715 if (ret) {
716 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
717 goto unlock;
718 }
719
720 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
721 if (ret < 0) {
722 DRM_ERROR("Failed to pack infoframe: %d\n", ret);
723 goto unlock;
724 }
725
726 /* Write new AVI infoframe packet */
727 for (i = 0; i < HDMI_AVI_INFOFRAME_SIZE; i++) {
728 if (regmap_write(ctx->regmap, aviinfo_reg[i], buf[i + HDMI_INFOFRAME_HEADER_SIZE]))
729 goto unlock;
730 }
731 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
732 goto unlock;
733
734 /* Enable AVI infoframe */
735 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
736 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
737 goto unlock;
738
739 /* Set TX mode to HDMI */
740 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
741 goto unlock;
742
743 if (regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
744 IT66121_CLK_BANK_PWROFF_TXCLK, IT66121_CLK_BANK_PWROFF_TXCLK))
745 goto unlock;
746
747 if (it66121_configure_input(ctx))
748 goto unlock;
749
750 if (it66121_configure_afe(ctx, adjusted_mode))
751 goto unlock;
752
753 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, IT66121_CLK_BANK_PWROFF_TXCLK, 0);
754
755unlock:
756 mutex_unlock(&ctx->lock);
757}
758
759static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
760 const struct drm_display_info *info,
761 const struct drm_display_mode *mode)
762{
763 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
764 unsigned long max_clock;
765
766 max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
767
768 if (mode->clock > max_clock)
769 return MODE_CLOCK_HIGH;
770
771 if (mode->clock < 25000)
772 return MODE_CLOCK_LOW;
773
774 return MODE_OK;
775}
776
777static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge)
778{
779 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
780
781 return it66121_is_hpd_detect(ctx) ? connector_status_connected
782 : connector_status_disconnected;
783}
784
785static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
786{
787 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
788 int ret;
789
790 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
791 if (ret)
792 dev_err(ctx->dev, "failed to enable HPD IRQ\n");
793}
794
795static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
796{
797 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
798 int ret;
799
800 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
801 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
802 if (ret)
803 dev_err(ctx->dev, "failed to disable HPD IRQ\n");
804}
805
806static struct edid *it66121_bridge_get_edid(struct drm_bridge *bridge,
807 struct drm_connector *connector)
808{
809 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
810 struct edid *edid;
811
812 mutex_lock(&ctx->lock);
813 edid = drm_do_get_edid(connector, it66121_get_edid_block, ctx);
814 mutex_unlock(&ctx->lock);
815
816 return edid;
817}
818
819static const struct drm_bridge_funcs it66121_bridge_funcs = {
820 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
821 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
822 .atomic_reset = drm_atomic_helper_bridge_reset,
823 .attach = it66121_bridge_attach,
824 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
825 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
826 .atomic_enable = it66121_bridge_enable,
827 .atomic_disable = it66121_bridge_disable,
828 .mode_set = it66121_bridge_mode_set,
829 .mode_valid = it66121_bridge_mode_valid,
830 .detect = it66121_bridge_detect,
831 .get_edid = it66121_bridge_get_edid,
832 .hpd_enable = it66121_bridge_hpd_enable,
833 .hpd_disable = it66121_bridge_hpd_disable,
834};
835
836static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
837{
838 int ret;
839 unsigned int val;
840 struct it66121_ctx *ctx = dev_id;
841 struct device *dev = ctx->dev;
842 enum drm_connector_status status;
843 bool event = false;
844
845 mutex_lock(&ctx->lock);
846
847 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
848 if (ret)
849 goto unlock;
850
851 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
852 goto unlock;
853
854 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
855 if (ret) {
856 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
857 } else {
858 if (val & IT66121_INT_STATUS1_DDC_FIFOERR)
859 it66121_clear_ddc_fifo(ctx);
860 if (val & (IT66121_INT_STATUS1_DDC_BUSHANG |
861 IT66121_INT_STATUS1_DDC_NOACK))
862 it66121_abort_ddc_ops(ctx);
863 if (val & IT66121_INT_STATUS1_HPD_STATUS) {
864 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
865 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
866
867 status = it66121_is_hpd_detect(ctx) ? connector_status_connected
868 : connector_status_disconnected;
869
870 event = true;
871 }
872 }
873
874 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
875 IT66121_SYS_STATUS_CLEAR_IRQ,
876 IT66121_SYS_STATUS_CLEAR_IRQ);
877
878unlock:
879 mutex_unlock(&ctx->lock);
880
881 if (event)
882 drm_bridge_hpd_notify(&ctx->bridge, status);
883
884 return IRQ_HANDLED;
885}
886
887static int it66121_probe(struct i2c_client *client,
888 const struct i2c_device_id *id)
889{
890 u32 vendor_ids[2], device_ids[2], revision_id;
891 struct device_node *ep;
892 int ret;
893 struct it66121_ctx *ctx;
894 struct device *dev = &client->dev;
895
896 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
897 dev_err(dev, "I2C check functionality failed.\n");
898 return -ENXIO;
899 }
900
901 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
902 if (!ctx)
903 return -ENOMEM;
904
905 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
906 if (!ep)
907 return -EINVAL;
908
909 ctx->dev = dev;
910 ctx->client = client;
911
912 of_property_read_u32(ep, "bus-width", &ctx->bus_width);
913 of_node_put(ep);
914
915 if (ctx->bus_width != 12 && ctx->bus_width != 24)
916 return -EINVAL;
917
918 ep = of_graph_get_remote_node(dev->of_node, 1, -1);
919 if (!ep)
920 return -EPROBE_DEFER;
921
922 ctx->next_bridge = of_drm_find_bridge(ep);
923 of_node_put(ep);
924
925 i2c_set_clientdata(client, ctx);
926 mutex_init(&ctx->lock);
927
928 ctx->supplies[0].supply = "vcn33";
929 ctx->supplies[1].supply = "vcn18";
930 ctx->supplies[2].supply = "vrf12";
931 ret = devm_regulator_bulk_get(ctx->dev, 3, ctx->supplies);
932 if (ret) {
933 dev_err(ctx->dev, "regulator_bulk failed\n");
934 return ret;
935 }
936
937 ret = ite66121_power_on(ctx);
938 if (ret)
939 return ret;
940
941 it66121_hw_reset(ctx);
942
943 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
944 if (IS_ERR(ctx->regmap)) {
945 ite66121_power_off(ctx);
946 return PTR_ERR(ctx->regmap);
947 }
948
949 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
950 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
951 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
952 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
953
954 /* Revision is shared with DEVICE_ID1 */
955 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
956 device_ids[1] &= IT66121_DEVICE_ID1_MASK;
957
958 if (vendor_ids[0] != IT66121_VENDOR_ID0 || vendor_ids[1] != IT66121_VENDOR_ID1 ||
959 device_ids[0] != IT66121_DEVICE_ID0 || device_ids[1] != IT66121_DEVICE_ID1) {
960 ite66121_power_off(ctx);
961 return -ENODEV;
962 }
963
964 ctx->bridge.funcs = &it66121_bridge_funcs;
965 ctx->bridge.of_node = dev->of_node;
966 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
967 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
968
969 ret = devm_request_threaded_irq(dev, client->irq, NULL, it66121_irq_threaded_handler,
970 IRQF_ONESHOT, dev_name(dev), ctx);
971 if (ret < 0) {
972 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
973 ite66121_power_off(ctx);
974 return ret;
975 }
976
977 drm_bridge_add(&ctx->bridge);
978
979 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
980
981 return 0;
982}
983
984static int it66121_remove(struct i2c_client *client)
985{
986 struct it66121_ctx *ctx = i2c_get_clientdata(client);
987
988 ite66121_power_off(ctx);
989 drm_bridge_remove(&ctx->bridge);
990 mutex_destroy(&ctx->lock);
991
992 return 0;
993}
994
995static const struct of_device_id it66121_dt_match[] = {
996 { .compatible = "ite,it66121" },
997 { }
998};
999MODULE_DEVICE_TABLE(of, it66121_dt_match);
1000
1001static const struct i2c_device_id it66121_id[] = {
1002 { "it66121", 0 },
1003 { }
1004};
1005MODULE_DEVICE_TABLE(i2c, it66121_id);
1006
1007static struct i2c_driver it66121_driver = {
1008 .driver = {
1009 .name = "it66121",
1010 .of_match_table = it66121_dt_match,
1011 },
1012 .probe = it66121_probe,
1013 .remove = it66121_remove,
1014 .id_table = it66121_id,
1015};
1016
1017module_i2c_driver(it66121_driver);
1018
1019MODULE_AUTHOR("Phong LE");
1020MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1021MODULE_LICENSE("GPL v2");