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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
12
13description:
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23properties:
24 compatible:
25 items:
26 - enum:
27 - sifive,fu540-c000-clint
28 - canaan,k210-clint
29 - const: sifive,clint0
30
31 description:
32 Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
33 Supported compatible strings are -
34 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
35 onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
36 CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
37 "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
38 integration tweaks.
39 Please refer to sifive-blocks-ip-versioning.txt for details
40
41 reg:
42 maxItems: 1
43
44 interrupts-extended:
45 minItems: 1
46
47additionalProperties: false
48
49required:
50 - compatible
51 - reg
52 - interrupts-extended
53
54examples:
55 - |
56 timer@2000000 {
57 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
58 interrupts-extended = <&cpu1intc 3 &cpu1intc 7
59 &cpu2intc 3 &cpu2intc 7
60 &cpu3intc 3 &cpu3intc 7
61 &cpu4intc 3 &cpu4intc 7>;
62 reg = <0x2000000 0x10000>;
63 };
64...